clk: cdce706: Constify parent names in clock init data (f3db6f16) · Commits · 戴 / test

drivers/clk/clk-cdce706.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -94,7 +94,7 @@ static const char * const cdce706_source_name[] = {
		"clk_in0", "clk_in1",
		};

		static const char *cdce706_clkin_name[] = {
		static const char * const cdce706_clkin_name[] = {
		"clk_in",
		};

		@@ -102,7 +102,7 @@ static const char * const cdce706_pll_name[] = {
		"pll1", "pll2", "pll3",
		};

		static const char *cdce706_divider_parent_name[] = {
		static const char * const cdce706_divider_parent_name[] = {
		"clk_in", "pll1", "pll2", "pll2", "pll3",
		};