x86/resctrl: Support CPUID enumeration of MBM counter width (f3d44f18) · Commits · 戴 / test

The original Memory Bandwidth Monitoring (MBM) architectural definition defines counters of up to 62 bits in the IA32_QM_CTR MSR while the first-generation MBM implementation uses statically defined 24 bit counters. Expand the MBM CPUID enumeration properties to include the MBM counter width. The previously undefined EAX output register contains, in bits [7:0], the MBM counter width encoded as an offset from 24 bits. Enumerating this property is only specified for Intel CPUs. Suggested-by:

Borislav Petkov <bp@suse.de> Signed-off-by:

Reinette Chatre <reinette.chatre@intel.com> Signed-off-by:

Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/afa3af2f753f6bc301fb743bc8944e749cb24afa.1588715690.git.reinette.chatre@intel.com

arch/x86/include/asm/processor.h

+2 −1

Original line number	Diff line number	Diff line
		@@ -113,9 +113,10 @@ struct cpuinfo_x86 {
		/* in KB - valid for CPUS which support this call: */
		unsigned int x86_cache_size;
		int x86_cache_alignment; /* In bytes */
		/* Cache QoS architectural values: */
		/* Cache QoS architectural values, valid only on the BSP: */
		int x86_cache_max_rmid; /* max index */
		int x86_cache_occ_scale; /* scale to bytes */
		int x86_cache_mbm_width_offset;
		int x86_power;
		unsigned long loops_per_jiffy;
		/* cpuid returned max cores value: */

arch/x86/kernel/cpu/resctrl/core.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -964,6 +964,7 @@ void resctrl_cpu_detect(struct cpuinfo_x86 *c)
		if (!cpu_has(c, X86_FEATURE_CQM_LLC)) {
		c->x86_cache_max_rmid = -1;
		c->x86_cache_occ_scale = -1;
		c->x86_cache_mbm_width_offset = -1;
		return;
		}

		@@ -980,6 +981,10 @@ void resctrl_cpu_detect(struct cpuinfo_x86 *c)

		c->x86_cache_max_rmid = ecx;
		c->x86_cache_occ_scale = ebx;
		if (c->x86_vendor == X86_VENDOR_INTEL)
		c->x86_cache_mbm_width_offset = eax & 0xff;
		else
		c->x86_cache_mbm_width_offset = -1;
		}
		}

Admin message