Commit f3c91098 authored by Bjorn Helgaas's avatar Bjorn Helgaas Committed by Bjorn Helgaas
Browse files

Merge branch 'lorenzo/pci/dwc' 

* lorenzo/pci/dwc:
  PCI: histb: Add an optional regulator for PCIe port power control
  PCI: histb: Fix error path of histb_pcie_host_enable()
  PCI: qcom: Use regulator bulk api for apq8064 supplies
  PCI: qcom: Add missing supplies required for msm8996
  PCI: designware-ep: Fix typo in error message
parents 248c51d9 58dfb243

Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt

+1 −0
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ Required properties 


Optional properties:

- reset-gpios: The gpio to generate PCIe PERST# assert and deassert signal.

- vpcie-supply: The regulator in charge of PCIe port power.

- phys: List of phandle and phy mode specifier, should be 0.

- phy-names: Must be "phy".

Documentation/devicetree/bindings/pci/qcom,pcie.txt

+4 −0
Original line number Diff line number Diff line
@@ -189,6 +189,10 @@ 
	Value type: <phandle>

	Definition: A phandle to the analog power supply for IC which generates

		    reference clock

- vddpe-3v3-supply:

	Usage: optional

	Value type: <phandle>

	Definition: A phandle to the PCIe endpoint power supply



- phys:

	Usage: required for apq8084

drivers/pci/dwc/pcie-designware-ep.c

+1 −1
Original line number Diff line number Diff line
@@ -322,7 +322,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) 
	struct device_node *np = dev->of_node;



	if (!pci->dbi_base || !pci->dbi_base2) {

		dev_err(dev, "dbi_base/deb_base2 is not populated\n");

		dev_err(dev, "dbi_base/dbi_base2 is not populated\n");

		return -EINVAL;

	}

drivers/pci/dwc/pcie-histb.c

+24 −4
Original line number Diff line number Diff line
@@ -61,6 +61,7 @@ struct histb_pcie { 
	struct reset_control *bus_reset;

	void __iomem *ctrl;

	int reset_gpio;

	struct regulator *vpcie;

};



static u32 histb_pcie_readl(struct histb_pcie *histb_pcie, u32 reg)
@@ -227,6 +228,9 @@ static void histb_pcie_host_disable(struct histb_pcie *hipcie) 


	if (gpio_is_valid(hipcie->reset_gpio))

		gpio_set_value_cansleep(hipcie->reset_gpio, 0);



	if (hipcie->vpcie)

		regulator_disable(hipcie->vpcie);

}



static int histb_pcie_host_enable(struct pcie_port *pp)
@@ -237,6 +241,14 @@ static int histb_pcie_host_enable(struct pcie_port *pp) 
	int ret;



	/* power on PCIe device if have */

	if (hipcie->vpcie) {

		ret = regulator_enable(hipcie->vpcie);

		if (ret) {

			dev_err(dev, "failed to enable regulator: %d\n", ret);

			return ret;

		}

	}



	if (gpio_is_valid(hipcie->reset_gpio))

		gpio_set_value_cansleep(hipcie->reset_gpio, 1);
@@ -276,13 +288,14 @@ static int histb_pcie_host_enable(struct pcie_port *pp) 
	return 0;



err_aux_clk:

	clk_disable_unprepare(hipcie->aux_clk);

err_pipe_clk:

	clk_disable_unprepare(hipcie->pipe_clk);

err_sys_clk:

err_pipe_clk:

	clk_disable_unprepare(hipcie->sys_clk);

err_bus_clk:

err_sys_clk:

	clk_disable_unprepare(hipcie->bus_clk);

err_bus_clk:

	if (hipcie->vpcie)

		regulator_disable(hipcie->vpcie);



	return ret;

}
@@ -332,6 +345,13 @@ static int histb_pcie_probe(struct platform_device *pdev) 
		return PTR_ERR(pci->dbi_base);

	}



	hipcie->vpcie = devm_regulator_get_optional(dev, "vpcie");

	if (IS_ERR(hipcie->vpcie)) {

		if (PTR_ERR(hipcie->vpcie) == -EPROBE_DEFER)

			return -EPROBE_DEFER;

		hipcie->vpcie = NULL;

	}



	hipcie->reset_gpio = of_get_named_gpio_flags(np,

				"reset-gpios", 0, &of_flags);

	if (of_flags & OF_GPIO_ACTIVE_LOW)

drivers/pci/dwc/pcie-qcom.c

+37 −38
Original line number Diff line number Diff line
@@ -79,6 +79,7 @@ 
#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE	0x358

#define SLV_ADDR_SPACE_SZ			0x10000000



#define QCOM_PCIE_2_1_0_MAX_SUPPLY	3

struct qcom_pcie_resources_2_1_0 {

	struct clk *iface_clk;

	struct clk *core_clk;
@@ -88,9 +89,7 @@ struct qcom_pcie_resources_2_1_0 { 
	struct reset_control *ahb_reset;

	struct reset_control *por_reset;

	struct reset_control *phy_reset;

	struct regulator *vdda;

	struct regulator *vdda_phy;

	struct regulator *vdda_refclk;

	struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];

};



struct qcom_pcie_resources_1_0_0 {
@@ -102,12 +101,14 @@ struct qcom_pcie_resources_1_0_0 { 
	struct regulator *vdda;

};



#define QCOM_PCIE_2_3_2_MAX_SUPPLY	2

struct qcom_pcie_resources_2_3_2 {

	struct clk *aux_clk;

	struct clk *master_clk;

	struct clk *slave_clk;

	struct clk *cfg_clk;

	struct clk *pipe_clk;

	struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY];

};



struct qcom_pcie_resources_2_4_0 {
@@ -216,18 +217,15 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) 
	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;

	struct dw_pcie *pci = pcie->pci;

	struct device *dev = pci->dev;

	int ret;



	res->vdda = devm_regulator_get(dev, "vdda");

	if (IS_ERR(res->vdda))

		return PTR_ERR(res->vdda);



	res->vdda_phy = devm_regulator_get(dev, "vdda_phy");

	if (IS_ERR(res->vdda_phy))

		return PTR_ERR(res->vdda_phy);



	res->vdda_refclk = devm_regulator_get(dev, "vdda_refclk");

	if (IS_ERR(res->vdda_refclk))

		return PTR_ERR(res->vdda_refclk);

	res->supplies[0].supply = "vdda";

	res->supplies[1].supply = "vdda_phy";

	res->supplies[2].supply = "vdda_refclk";

	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),

				      res->supplies);

	if (ret)

		return ret;



	res->iface_clk = devm_clk_get(dev, "iface");

	if (IS_ERR(res->iface_clk))
@@ -273,9 +271,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) 
	clk_disable_unprepare(res->iface_clk);

	clk_disable_unprepare(res->core_clk);

	clk_disable_unprepare(res->phy_clk);

	regulator_disable(res->vdda);

	regulator_disable(res->vdda_phy);

	regulator_disable(res->vdda_refclk);

	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);

}



static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
@@ -286,24 +282,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) 
	u32 val;

	int ret;



	ret = regulator_enable(res->vdda);

	if (ret) {

		dev_err(dev, "cannot enable vdda regulator\n");

	ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);

	if (ret < 0) {

		dev_err(dev, "cannot enable regulators\n");

		return ret;

	}



	ret = regulator_enable(res->vdda_refclk);

	if (ret) {

		dev_err(dev, "cannot enable vdda_refclk regulator\n");

		goto err_refclk;

	}



	ret = regulator_enable(res->vdda_phy);

	if (ret) {

		dev_err(dev, "cannot enable vdda_phy regulator\n");

		goto err_vdda_phy;

	}



	ret = reset_control_assert(res->ahb_reset);

	if (ret) {

		dev_err(dev, "cannot assert ahb reset\n");
@@ -387,11 +371,7 @@ err_clk_core: 
err_clk_phy:

	clk_disable_unprepare(res->iface_clk);

err_assert_ahb:

	regulator_disable(res->vdda_phy);

err_vdda_phy:

	regulator_disable(res->vdda_refclk);

err_refclk:

	regulator_disable(res->vdda);

	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);



	return ret;

}
@@ -521,6 +501,14 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) 
	struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;

	struct dw_pcie *pci = pcie->pci;

	struct device *dev = pci->dev;

	int ret;



	res->supplies[0].supply = "vdda";

	res->supplies[1].supply = "vddpe-3v3";

	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),

				      res->supplies);

	if (ret)

		return ret;



	res->aux_clk = devm_clk_get(dev, "aux");

	if (IS_ERR(res->aux_clk))
@@ -550,6 +538,8 @@ static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) 
	clk_disable_unprepare(res->master_clk);

	clk_disable_unprepare(res->cfg_clk);

	clk_disable_unprepare(res->aux_clk);



	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);

}



static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie)
@@ -567,10 +557,16 @@ static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) 
	u32 val;

	int ret;



	ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);

	if (ret < 0) {

		dev_err(dev, "cannot enable regulators\n");

		return ret;

	}



	ret = clk_prepare_enable(res->aux_clk);

	if (ret) {

		dev_err(dev, "cannot prepare/enable aux clock\n");

		return ret;

		goto err_aux_clk;

	}



	ret = clk_prepare_enable(res->cfg_clk);
@@ -621,6 +617,9 @@ err_master_clk: 
err_cfg_clk:

	clk_disable_unprepare(res->aux_clk);



err_aux_clk:

	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);



	return ret;

}

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