Commit f3a186fb authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'imx-soc-4.6' of... 

Merge tag 'imx-soc-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc

Merge "i.MX SoC update for 4.6" from Shawn Guo:

- Enable big endian mode support for i.MX platform
- Add support for i.MX6QP SoC which is the latest i.MX6 family addition
- Add basic suspend/resume support for i.MX25
- A couple of i.MX7D support updates
- A few random code cleanups

* tag 'imx-soc-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: imx: Make reset_control_ops const
  ARM: imx: Do L2 errata only if the L2 cache isn't enabled
  ARM: imx: select ARM_CPU_SUSPEND only for imx6
  ARM: mx25: Add basic suspend/resume support
  ARM: imx: Add msl code support for imx6qp
  ARM: imx: enable big endian mode
  ARM: imx: use endian-safe readl/readw/writel/writew
  ARM: imx7d: correct chip version information
  ARM: imx: select HAVE_ARM_ARCH_TIMER if selected i.MX7D
  ARM: imx6: fix cleanup path in imx6q_suspend_init()
parents e91fb3bd d2443b2e

arch/arm/include/debug/imx.S

+3 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
 *

 */



#include <asm/assembler.h>

#include "imx-uart.h"



/*
@@ -34,6 +35,7 @@ 
		.endm



		.macro	senduart,rd,rx

		ARM_BE8(rev \rd, \rd)

		str	\rd, [\rx, #0x40]	@ TXDATA

		.endm
@@ -42,6 +44,7 @@ 


		.macro	busyuart,rd,rx

1002:		ldr	\rd, [\rx, #0x98]	@ SR2

		ARM_BE8(rev \rd, \rd)

		tst	\rd, #1 << 3		@ TXDC

		beq	1002b			@ wait until transmit done

		.endm

arch/arm/mach-imx/3ds_debugboard.c

+15 −15
Original line number Diff line number Diff line
@@ -94,8 +94,8 @@ static void mxc_expio_irq_handler(struct irq_desc *desc) 
	/* irq = gpio irq number */

	desc->irq_data.chip->irq_mask(&desc->irq_data);



	imr_val = __raw_readw(brd_io + INTR_MASK_REG);

	int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;

	imr_val = imx_readw(brd_io + INTR_MASK_REG);

	int_valid = imx_readw(brd_io + INTR_STATUS_REG) & ~imr_val;



	expio_irq = 0;

	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
@@ -117,17 +117,17 @@ static void expio_mask_irq(struct irq_data *d) 
	u16 reg;

	u32 expio = d->hwirq;



	reg = __raw_readw(brd_io + INTR_MASK_REG);

	reg = imx_readw(brd_io + INTR_MASK_REG);

	reg |= (1 << expio);

	__raw_writew(reg, brd_io + INTR_MASK_REG);

	imx_writew(reg, brd_io + INTR_MASK_REG);

}



static void expio_ack_irq(struct irq_data *d)

{

	u32 expio = d->hwirq;



	__raw_writew(1 << expio, brd_io + INTR_RESET_REG);

	__raw_writew(0, brd_io + INTR_RESET_REG);

	imx_writew(1 << expio, brd_io + INTR_RESET_REG);

	imx_writew(0, brd_io + INTR_RESET_REG);

	expio_mask_irq(d);

}
@@ -136,9 +136,9 @@ static void expio_unmask_irq(struct irq_data *d) 
	u16 reg;

	u32 expio = d->hwirq;



	reg = __raw_readw(brd_io + INTR_MASK_REG);

	reg = imx_readw(brd_io + INTR_MASK_REG);

	reg &= ~(1 << expio);

	__raw_writew(reg, brd_io + INTR_MASK_REG);

	imx_writew(reg, brd_io + INTR_MASK_REG);

}



static struct irq_chip expio_irq_chip = {
@@ -162,9 +162,9 @@ int __init mxc_expio_init(u32 base, u32 intr_gpio) 
	if (brd_io == NULL)

		return -ENOMEM;



	if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||

	    (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||

	    (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {

	if ((imx_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||

	    (imx_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||

	    (imx_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {

		pr_info("3-Stack Debug board not detected\n");

		iounmap(brd_io);

		brd_io = NULL;
@@ -181,10 +181,10 @@ int __init mxc_expio_init(u32 base, u32 intr_gpio) 
	gpio_direction_input(intr_gpio);



	/* disable the interrupt and clear the status */

	__raw_writew(0, brd_io + INTR_MASK_REG);

	__raw_writew(0xFFFF, brd_io + INTR_RESET_REG);

	__raw_writew(0, brd_io + INTR_RESET_REG);

	__raw_writew(0x1F, brd_io + INTR_MASK_REG);

	imx_writew(0, brd_io + INTR_MASK_REG);

	imx_writew(0xFFFF, brd_io + INTR_RESET_REG);

	imx_writew(0, brd_io + INTR_RESET_REG);

	imx_writew(0x1F, brd_io + INTR_MASK_REG);



	irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());

	WARN_ON(irq_base < 0);

arch/arm/mach-imx/Kconfig

+3 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ menuconfig ARCH_MXC 
	bool "Freescale i.MX family"

	depends on ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7 || ARM_SINGLE_ARMV7M

	select ARCH_REQUIRE_GPIOLIB

	select ARM_CPU_SUSPEND if PM

	select ARCH_SUPPORTS_BIG_ENDIAN

	select CLKSRC_IMX_GPT

	select GENERIC_IRQ_CHIP

	select PINCTRL
@@ -511,6 +511,7 @@ config SOC_IMX53 


config SOC_IMX6

	bool

	select ARM_CPU_SUSPEND if PM

	select ARM_ERRATA_754322

	select ARM_ERRATA_775420

	select ARM_GIC
@@ -561,6 +562,7 @@ config SOC_IMX7D 
	bool "i.MX7 Dual support"

	select PINCTRL_IMX7D

	select ARM_GIC

	select HAVE_ARM_ARCH_TIMER

	select HAVE_IMX_ANATOP

	select HAVE_IMX_MMDC

	select HAVE_IMX_SRC

arch/arm/mach-imx/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ obj-y := cpu.o system.o irq-common.o 
obj-$(CONFIG_SOC_IMX1) += mm-imx1.o

obj-$(CONFIG_SOC_IMX21) += mm-imx21.o



obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o

obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o



obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o

obj-$(CONFIG_SOC_IMX27) += mm-imx27.o ehci-imx27.o

arch/arm/mach-imx/anatop.c

+16 −2
Original line number Diff line number Diff line
@@ -129,6 +129,13 @@ void __init imx_init_revision_from_anatop(void) 


	switch (digprog & 0xff) {

	case 0:

		/*

		 * For i.MX6QP, most of the code for i.MX6Q can be resued,

		 * so internally, we identify it as i.MX6Q Rev 2.0

		 */

		if (digprog >> 8 & 0x01)

			revision = IMX_CHIP_REVISION_2_0;

		else

			revision = IMX_CHIP_REVISION_1_0;

		break;

	case 1:
@@ -151,7 +158,14 @@ void __init imx_init_revision_from_anatop(void) 
		revision = IMX_CHIP_REVISION_1_5;

		break;

	default:

		revision = IMX_CHIP_REVISION_UNKNOWN;

		/*

		 * Fail back to return raw register value instead of 0xff.

		 * It will be easy to know version information in SOC if it

		 * can't be recognized by known version. And some chip's (i.MX7D)

		 * digprog value match linux version format, so it needn't map

		 * again and we can use register value directly.

		 */

		revision = digprog & 0xff;

	}



	mxc_set_cpu_type(digprog >> 16 & 0xff);

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