Commit f3a02ece authored by Bin Gao's avatar Bin Gao Committed by Thomas Gleixner
Browse files

x86/tsc: Set TSC_KNOWN_FREQ and TSC_RELIABLE flags on Intel Atom SoCs 



TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is
reliable and the frequency is known (provided by HW).

On these platforms PIT/HPET is generally not available so calibration won't
work at all and there is no other clocksource to act as a watchdog for the
TSC, so we have no other choice than to trust it.

Set both X86_FEATURE_TSC_KNOWN_FREQ and X86_FEATURE_TSC_RELIABLE flags to
make sure the calibration is skipped and no watchdog is required.

Signed-off-by: default avatarBin Gao <bin.gao@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1479241644-234277-5-git-send-email-bin.gao@linux.intel.com


Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 4635fdc6

arch/x86/kernel/tsc_msr.c

+19 −0
Original line number Original line Diff line number Diff line
@@ -100,5 +100,24 @@ unsigned long cpu_khz_from_msr(void) 
#ifdef CONFIG_X86_LOCAL_APIC

#ifdef CONFIG_X86_LOCAL_APIC

	lapic_timer_frequency = (freq * 1000) / HZ;

	lapic_timer_frequency = (freq * 1000) / HZ;

#endif

#endif



	/*

	 * TSC frequency determined by MSR is always considered "known"

	 * because it is reported by HW.

	 * Another fact is that on MSR capable platforms, PIT/HPET is

	 * generally not available so calibration won't work at all.

	 */

	setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);



	/*

	 * Unfortunately there is no way for hardware to tell whether the

	 * TSC is reliable.  We were told by silicon design team that TSC

	 * on Atom SoCs are always "reliable". TSC is also the only

	 * reliable clocksource on these SoCs (HPET is either not present

	 * or not functional) so mark TSC reliable which removes the

	 * requirement for a watchdog clocksource.

	 */

	setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);



	return res;

	return res;

}
 
}

arch/x86/platform/intel-mid/mfld.c

+7 −2
Original line number Original line Diff line number Diff line
@@ -49,8 +49,13 @@ static unsigned long __init mfld_calibrate_tsc(void) 
	fast_calibrate = ratio * fsb;

	fast_calibrate = ratio * fsb;

	pr_debug("read penwell tsc %lu khz\n", fast_calibrate);

	pr_debug("read penwell tsc %lu khz\n", fast_calibrate);

	lapic_timer_frequency = fsb * 1000 / HZ;

	lapic_timer_frequency = fsb * 1000 / HZ;

	/* mark tsc clocksource as reliable */



	set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);

	/*

	 * TSC on Intel Atom SoCs is reliable and of known frequency.

	 * See tsc_msr.c for details.

	 */

	setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);

	setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);





	return fast_calibrate;

	return fast_calibrate;

}

}

arch/x86/platform/intel-mid/mrfld.c

+6 −2
Original line number Original line Diff line number Diff line
@@ -78,8 +78,12 @@ static unsigned long __init tangier_calibrate_tsc(void) 
	pr_debug("Setting lapic_timer_frequency = %d\n",

	pr_debug("Setting lapic_timer_frequency = %d\n",

			lapic_timer_frequency);

			lapic_timer_frequency);





	/* mark tsc clocksource as reliable */

	/*

	set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);

	 * TSC on Intel Atom SoCs is reliable and of known frequency.

	 * See tsc_msr.c for details.

	 */

	setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);

	setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);





	return fast_calibrate;

	return fast_calibrate;

}

}

CRA Git | Maintained and supported by SUSTech CRA and CCSE