Commit f38ca10a authored by Paul Walmsley's avatar Paul Walmsley
Browse files

OMAP2 PRCM: convert OMAP2 PRCM macros to the _SHIFT/_MASK suffixes 



Fix all of the remaining OMAP2 PRCM register shift/bitmask macros that
did not use the _SHIFT/_MASK suffixes to use them.  This makes the use
of these macros consistent.  It is intended to reduce error, as code
can be inspected visually by reviewers to ensure that bitshifts and
bitmasks are used in the appropriate places.

Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
parent 5838bb67

arch/arm/mach-omap2/clkt2xxx_apll.c

+2 −2
Original line number Diff line number Diff line
@@ -70,12 +70,12 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) 


static int omap2_clk_apll96_enable(struct clk *clk)

{

	return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL);

	return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL_MASK);

}



static int omap2_clk_apll54_enable(struct clk *clk)

{

	return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL);

	return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK);

}



/* Stop APLL */

arch/arm/mach-omap2/clock2420_data.c

+2 −2
Original line number Diff line number Diff line
@@ -177,7 +177,7 @@ static struct clk func_54m_ck = { 
	.clkdm_name	= "wkup_clkdm",

	.init		= &omap2_init_clksel_parent,

	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),

	.clksel_mask	= OMAP24XX_54M_SOURCE,

	.clksel_mask	= OMAP24XX_54M_SOURCE_MASK,

	.clksel		= func_54m_clksel,

	.recalc		= &omap2_clksel_recalc,

};
@@ -223,7 +223,7 @@ static struct clk func_48m_ck = { 
	.clkdm_name	= "wkup_clkdm",

	.init		= &omap2_init_clksel_parent,

	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),

	.clksel_mask	= OMAP24XX_48M_SOURCE,

	.clksel_mask	= OMAP24XX_48M_SOURCE_MASK,

	.clksel		= func_48m_clksel,

	.recalc		= &omap2_clksel_recalc,

	.round_rate	= &omap2_clksel_round_rate,

arch/arm/mach-omap2/clock2430_data.c

+3 −3
Original line number Diff line number Diff line
@@ -177,7 +177,7 @@ static struct clk func_54m_ck = { 
	.clkdm_name	= "wkup_clkdm",

	.init		= &omap2_init_clksel_parent,

	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),

	.clksel_mask	= OMAP24XX_54M_SOURCE,

	.clksel_mask	= OMAP24XX_54M_SOURCE_MASK,

	.clksel		= func_54m_clksel,

	.recalc		= &omap2_clksel_recalc,

};
@@ -214,7 +214,7 @@ static struct clk func_96m_ck = { 
	.clkdm_name	= "wkup_clkdm",

	.init		= &omap2_init_clksel_parent,

	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),

	.clksel_mask	= OMAP2430_96M_SOURCE,

	.clksel_mask	= OMAP2430_96M_SOURCE_MASK,

	.clksel		= func_96m_clksel,

	.recalc		= &omap2_clksel_recalc,

};
@@ -244,7 +244,7 @@ static struct clk func_48m_ck = { 
	.clkdm_name	= "wkup_clkdm",

	.init		= &omap2_init_clksel_parent,

	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),

	.clksel_mask	= OMAP24XX_48M_SOURCE,

	.clksel_mask	= OMAP24XX_48M_SOURCE_MASK,

	.clksel		= func_48m_clksel,

	.recalc		= &omap2_clksel_recalc,

	.round_rate	= &omap2_clksel_round_rate,

arch/arm/mach-omap2/clockdomain.c

+2 −2
Original line number Diff line number Diff line
@@ -809,7 +809,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm) 


	if (cpu_is_omap24xx()) {



		cm_set_mod_reg_bits(OMAP24XX_FORCESTATE,

		cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,

			    clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);



	} else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
@@ -853,7 +853,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm) 


	if (cpu_is_omap24xx()) {



		cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE,

		cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,

			      clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);



	} else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {

arch/arm/mach-omap2/cm-regbits-24xx.h

+118 −118
Original line number Diff line number Diff line
@@ -20,43 +20,43 @@ 


/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */

#define OMAP24XX_EN_CAM_SHIFT				31

#define OMAP24XX_EN_CAM					(1 << 31)

#define OMAP24XX_EN_CAM_MASK				(1 << 31)

#define OMAP24XX_EN_WDT4_SHIFT				29

#define OMAP24XX_EN_WDT4				(1 << 29)

#define OMAP24XX_EN_WDT4_MASK				(1 << 29)

#define OMAP2420_EN_WDT3_SHIFT				28

#define OMAP2420_EN_WDT3				(1 << 28)

#define OMAP2420_EN_WDT3_MASK				(1 << 28)

#define OMAP24XX_EN_MSPRO_SHIFT				27

#define OMAP24XX_EN_MSPRO				(1 << 27)

#define OMAP24XX_EN_MSPRO_MASK				(1 << 27)

#define OMAP24XX_EN_FAC_SHIFT				25

#define OMAP24XX_EN_FAC					(1 << 25)

#define OMAP24XX_EN_FAC_MASK				(1 << 25)

#define OMAP2420_EN_EAC_SHIFT				24

#define OMAP2420_EN_EAC					(1 << 24)

#define OMAP2420_EN_EAC_MASK				(1 << 24)

#define OMAP24XX_EN_HDQ_SHIFT				23

#define OMAP24XX_EN_HDQ					(1 << 23)

#define OMAP24XX_EN_HDQ_MASK				(1 << 23)

#define OMAP2420_EN_I2C2_SHIFT				20

#define OMAP2420_EN_I2C2				(1 << 20)

#define OMAP2420_EN_I2C2_MASK				(1 << 20)

#define OMAP2420_EN_I2C1_SHIFT				19

#define OMAP2420_EN_I2C1				(1 << 19)

#define OMAP2420_EN_I2C1_MASK				(1 << 19)



/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */

#define OMAP2430_EN_MCBSP5_SHIFT			5

#define OMAP2430_EN_MCBSP5				(1 << 5)

#define OMAP2430_EN_MCBSP5_MASK				(1 << 5)

#define OMAP2430_EN_MCBSP4_SHIFT			4

#define OMAP2430_EN_MCBSP4				(1 << 4)

#define OMAP2430_EN_MCBSP4_MASK				(1 << 4)

#define OMAP2430_EN_MCBSP3_SHIFT			3

#define OMAP2430_EN_MCBSP3				(1 << 3)

#define OMAP2430_EN_MCBSP3_MASK				(1 << 3)

#define OMAP24XX_EN_SSI_SHIFT				1

#define OMAP24XX_EN_SSI					(1 << 1)

#define OMAP24XX_EN_SSI_MASK				(1 << 1)



/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */

#define OMAP24XX_EN_MPU_WDT_SHIFT			3

#define OMAP24XX_EN_MPU_WDT				(1 << 3)

#define OMAP24XX_EN_MPU_WDT_MASK			(1 << 3)



/* Bits specific to each register */



/* CM_IDLEST_MPU */

/* 2430 only */

#define OMAP2430_ST_MPU					(1 << 0)

#define OMAP2430_ST_MPU_MASK				(1 << 0)



/* CM_CLKSEL_MPU */

#define OMAP24XX_CLKSEL_MPU_SHIFT			0
@@ -68,46 +68,46 @@ 


/* CM_FCLKEN1_CORE specific bits*/

#define OMAP24XX_EN_TV_SHIFT				2

#define OMAP24XX_EN_TV					(1 << 2)

#define OMAP24XX_EN_TV_MASK				(1 << 2)

#define OMAP24XX_EN_DSS2_SHIFT				1

#define OMAP24XX_EN_DSS2				(1 << 1)

#define OMAP24XX_EN_DSS2_MASK				(1 << 1)

#define OMAP24XX_EN_DSS1_SHIFT				0

#define OMAP24XX_EN_DSS1				(1 << 0)

#define OMAP24XX_EN_DSS1_MASK				(1 << 0)



/* CM_FCLKEN2_CORE specific bits */

#define OMAP2430_EN_I2CHS2_SHIFT			20

#define OMAP2430_EN_I2CHS2				(1 << 20)

#define OMAP2430_EN_I2CHS2_MASK				(1 << 20)

#define OMAP2430_EN_I2CHS1_SHIFT			19

#define OMAP2430_EN_I2CHS1				(1 << 19)

#define OMAP2430_EN_I2CHS1_MASK				(1 << 19)

#define OMAP2430_EN_MMCHSDB2_SHIFT			17

#define OMAP2430_EN_MMCHSDB2				(1 << 17)

#define OMAP2430_EN_MMCHSDB2_MASK			(1 << 17)

#define OMAP2430_EN_MMCHSDB1_SHIFT			16

#define OMAP2430_EN_MMCHSDB1				(1 << 16)

#define OMAP2430_EN_MMCHSDB1_MASK			(1 << 16)



/* CM_ICLKEN1_CORE specific bits */

#define OMAP24XX_EN_MAILBOXES_SHIFT			30

#define OMAP24XX_EN_MAILBOXES				(1 << 30)

#define OMAP24XX_EN_MAILBOXES_MASK			(1 << 30)

#define OMAP24XX_EN_DSS_SHIFT				0

#define OMAP24XX_EN_DSS					(1 << 0)

#define OMAP24XX_EN_DSS_MASK				(1 << 0)



/* CM_ICLKEN2_CORE specific bits */



/* CM_ICLKEN3_CORE */

/* 2430 only */

#define OMAP2430_EN_SDRC_SHIFT				2

#define OMAP2430_EN_SDRC				(1 << 2)

#define OMAP2430_EN_SDRC_MASK				(1 << 2)



/* CM_ICLKEN4_CORE */

#define OMAP24XX_EN_PKA_SHIFT				4

#define OMAP24XX_EN_PKA					(1 << 4)

#define OMAP24XX_EN_PKA_MASK				(1 << 4)

#define OMAP24XX_EN_AES_SHIFT				3

#define OMAP24XX_EN_AES					(1 << 3)

#define OMAP24XX_EN_AES_MASK				(1 << 3)

#define OMAP24XX_EN_RNG_SHIFT				2

#define OMAP24XX_EN_RNG					(1 << 2)

#define OMAP24XX_EN_RNG_MASK				(1 << 2)

#define OMAP24XX_EN_SHA_SHIFT				1

#define OMAP24XX_EN_SHA					(1 << 1)

#define OMAP24XX_EN_SHA_MASK				(1 << 1)

#define OMAP24XX_EN_DES_SHIFT				0

#define OMAP24XX_EN_DES					(1 << 0)

#define OMAP24XX_EN_DES_MASK				(1 << 0)



/* CM_IDLEST1_CORE specific bits */

#define OMAP24XX_ST_MAILBOXES_SHIFT			30
@@ -162,62 +162,62 @@ 
#define OMAP24XX_ST_DES_MASK				(1 << 0)



/* CM_AUTOIDLE1_CORE */

#define OMAP24XX_AUTO_CAM				(1 << 31)

#define OMAP24XX_AUTO_MAILBOXES				(1 << 30)

#define OMAP24XX_AUTO_WDT4				(1 << 29)

#define OMAP2420_AUTO_WDT3				(1 << 28)

#define OMAP24XX_AUTO_MSPRO				(1 << 27)

#define OMAP2420_AUTO_MMC				(1 << 26)

#define OMAP24XX_AUTO_FAC				(1 << 25)

#define OMAP2420_AUTO_EAC				(1 << 24)

#define OMAP24XX_AUTO_HDQ				(1 << 23)

#define OMAP24XX_AUTO_UART2				(1 << 22)

#define OMAP24XX_AUTO_UART1				(1 << 21)

#define OMAP24XX_AUTO_I2C2				(1 << 20)

#define OMAP24XX_AUTO_I2C1				(1 << 19)

#define OMAP24XX_AUTO_MCSPI2				(1 << 18)

#define OMAP24XX_AUTO_MCSPI1				(1 << 17)

#define OMAP24XX_AUTO_MCBSP2				(1 << 16)

#define OMAP24XX_AUTO_MCBSP1				(1 << 15)

#define OMAP24XX_AUTO_GPT12				(1 << 14)

#define OMAP24XX_AUTO_GPT11				(1 << 13)

#define OMAP24XX_AUTO_GPT10				(1 << 12)

#define OMAP24XX_AUTO_GPT9				(1 << 11)

#define OMAP24XX_AUTO_GPT8				(1 << 10)

#define OMAP24XX_AUTO_GPT7				(1 << 9)

#define OMAP24XX_AUTO_GPT6				(1 << 8)

#define OMAP24XX_AUTO_GPT5				(1 << 7)

#define OMAP24XX_AUTO_GPT4				(1 << 6)

#define OMAP24XX_AUTO_GPT3				(1 << 5)

#define OMAP24XX_AUTO_GPT2				(1 << 4)

#define OMAP2420_AUTO_VLYNQ				(1 << 3)

#define OMAP24XX_AUTO_DSS				(1 << 0)

#define OMAP24XX_AUTO_CAM_MASK				(1 << 31)

#define OMAP24XX_AUTO_MAILBOXES_MASK			(1 << 30)

#define OMAP24XX_AUTO_WDT4_MASK				(1 << 29)

#define OMAP2420_AUTO_WDT3_MASK				(1 << 28)

#define OMAP24XX_AUTO_MSPRO_MASK			(1 << 27)

#define OMAP2420_AUTO_MMC_MASK				(1 << 26)

#define OMAP24XX_AUTO_FAC_MASK				(1 << 25)

#define OMAP2420_AUTO_EAC_MASK				(1 << 24)

#define OMAP24XX_AUTO_HDQ_MASK				(1 << 23)

#define OMAP24XX_AUTO_UART2_MASK			(1 << 22)

#define OMAP24XX_AUTO_UART1_MASK			(1 << 21)

#define OMAP24XX_AUTO_I2C2_MASK				(1 << 20)

#define OMAP24XX_AUTO_I2C1_MASK				(1 << 19)

#define OMAP24XX_AUTO_MCSPI2_MASK			(1 << 18)

#define OMAP24XX_AUTO_MCSPI1_MASK			(1 << 17)

#define OMAP24XX_AUTO_MCBSP2_MASK			(1 << 16)

#define OMAP24XX_AUTO_MCBSP1_MASK			(1 << 15)

#define OMAP24XX_AUTO_GPT12_MASK			(1 << 14)

#define OMAP24XX_AUTO_GPT11_MASK			(1 << 13)

#define OMAP24XX_AUTO_GPT10_MASK			(1 << 12)

#define OMAP24XX_AUTO_GPT9_MASK				(1 << 11)

#define OMAP24XX_AUTO_GPT8_MASK				(1 << 10)

#define OMAP24XX_AUTO_GPT7_MASK				(1 << 9)

#define OMAP24XX_AUTO_GPT6_MASK				(1 << 8)

#define OMAP24XX_AUTO_GPT5_MASK				(1 << 7)

#define OMAP24XX_AUTO_GPT4_MASK				(1 << 6)

#define OMAP24XX_AUTO_GPT3_MASK				(1 << 5)

#define OMAP24XX_AUTO_GPT2_MASK				(1 << 4)

#define OMAP2420_AUTO_VLYNQ_MASK			(1 << 3)

#define OMAP24XX_AUTO_DSS_MASK				(1 << 0)



/* CM_AUTOIDLE2_CORE */

#define OMAP2430_AUTO_MDM_INTC				(1 << 11)

#define OMAP2430_AUTO_GPIO5				(1 << 10)

#define OMAP2430_AUTO_MCSPI3				(1 << 9)

#define OMAP2430_AUTO_MMCHS2				(1 << 8)

#define OMAP2430_AUTO_MMCHS1				(1 << 7)

#define OMAP2430_AUTO_USBHS				(1 << 6)

#define OMAP2430_AUTO_MCBSP5				(1 << 5)

#define OMAP2430_AUTO_MCBSP4				(1 << 4)

#define OMAP2430_AUTO_MCBSP3				(1 << 3)

#define OMAP24XX_AUTO_UART3				(1 << 2)

#define OMAP24XX_AUTO_SSI				(1 << 1)

#define OMAP24XX_AUTO_USB				(1 << 0)

#define OMAP2430_AUTO_MDM_INTC_MASK			(1 << 11)

#define OMAP2430_AUTO_GPIO5_MASK			(1 << 10)

#define OMAP2430_AUTO_MCSPI3_MASK			(1 << 9)

#define OMAP2430_AUTO_MMCHS2_MASK			(1 << 8)

#define OMAP2430_AUTO_MMCHS1_MASK			(1 << 7)

#define OMAP2430_AUTO_USBHS_MASK			(1 << 6)

#define OMAP2430_AUTO_MCBSP5_MASK			(1 << 5)

#define OMAP2430_AUTO_MCBSP4_MASK			(1 << 4)

#define OMAP2430_AUTO_MCBSP3_MASK			(1 << 3)

#define OMAP24XX_AUTO_UART3_MASK			(1 << 2)

#define OMAP24XX_AUTO_SSI_MASK				(1 << 1)

#define OMAP24XX_AUTO_USB_MASK				(1 << 0)



/* CM_AUTOIDLE3_CORE */

#define OMAP24XX_AUTO_SDRC				(1 << 2)

#define OMAP24XX_AUTO_GPMC				(1 << 1)

#define OMAP24XX_AUTO_SDMA				(1 << 0)

#define OMAP24XX_AUTO_SDRC_MASK				(1 << 2)

#define OMAP24XX_AUTO_GPMC_MASK				(1 << 1)

#define OMAP24XX_AUTO_SDMA_MASK				(1 << 0)



/* CM_AUTOIDLE4_CORE */

#define OMAP24XX_AUTO_PKA				(1 << 4)

#define OMAP24XX_AUTO_AES				(1 << 3)

#define OMAP24XX_AUTO_RNG				(1 << 2)

#define OMAP24XX_AUTO_SHA				(1 << 1)

#define OMAP24XX_AUTO_DES				(1 << 0)

#define OMAP24XX_AUTO_PKA_MASK				(1 << 4)

#define OMAP24XX_AUTO_AES_MASK				(1 << 3)

#define OMAP24XX_AUTO_RNG_MASK				(1 << 2)

#define OMAP24XX_AUTO_SHA_MASK				(1 << 1)

#define OMAP24XX_AUTO_DES_MASK				(1 << 0)



/* CM_CLKSEL1_CORE */

#define OMAP24XX_CLKSEL_USB_SHIFT			25
@@ -269,9 +269,9 @@ 


/* CM_FCLKEN_GFX */

#define OMAP24XX_EN_3D_SHIFT				2

#define OMAP24XX_EN_3D					(1 << 2)

#define OMAP24XX_EN_3D_MASK				(1 << 2)

#define OMAP24XX_EN_2D_SHIFT				1

#define OMAP24XX_EN_2D					(1 << 1)

#define OMAP24XX_EN_2D_MASK				(1 << 1)



/* CM_ICLKEN_GFX specific bits */
@@ -287,13 +287,13 @@ 


/* CM_ICLKEN_WKUP specific bits */

#define OMAP2430_EN_ICR_SHIFT				6

#define OMAP2430_EN_ICR					(1 << 6)

#define OMAP2430_EN_ICR_MASK				(1 << 6)

#define OMAP24XX_EN_OMAPCTRL_SHIFT			5

#define OMAP24XX_EN_OMAPCTRL				(1 << 5)

#define OMAP24XX_EN_OMAPCTRL_MASK			(1 << 5)

#define OMAP24XX_EN_WDT1_SHIFT				4

#define OMAP24XX_EN_WDT1				(1 << 4)

#define OMAP24XX_EN_WDT1_MASK				(1 << 4)

#define OMAP24XX_EN_32KSYNC_SHIFT			1

#define OMAP24XX_EN_32KSYNC				(1 << 1)

#define OMAP24XX_EN_32KSYNC_MASK			(1 << 1)



/* CM_IDLEST_WKUP specific bits */

#define OMAP2430_ST_ICR_SHIFT				6
@@ -308,12 +308,12 @@ 
#define OMAP24XX_ST_32KSYNC_MASK			(1 << 1)



/* CM_AUTOIDLE_WKUP */

#define OMAP24XX_AUTO_OMAPCTRL				(1 << 5)

#define OMAP24XX_AUTO_WDT1				(1 << 4)

#define OMAP24XX_AUTO_MPU_WDT				(1 << 3)

#define OMAP24XX_AUTO_GPIOS				(1 << 2)

#define OMAP24XX_AUTO_32KSYNC				(1 << 1)

#define OMAP24XX_AUTO_GPT1				(1 << 0)

#define OMAP24XX_AUTO_OMAPCTRL_MASK			(1 << 5)

#define OMAP24XX_AUTO_WDT1_MASK				(1 << 4)

#define OMAP24XX_AUTO_MPU_WDT_MASK			(1 << 3)

#define OMAP24XX_AUTO_GPIOS_MASK			(1 << 2)

#define OMAP24XX_AUTO_32KSYNC_MASK			(1 << 1)

#define OMAP24XX_AUTO_GPT1_MASK				(1 << 0)



/* CM_CLKSEL_WKUP */

#define OMAP24XX_CLKSEL_GPT1_SHIFT			0
@@ -328,12 +328,12 @@ 
#define OMAP24XX_EN_DPLL_MASK				(0x3 << 0)



/* CM_IDLEST_CKGEN */

#define OMAP24XX_ST_54M_APLL				(1 << 9)

#define OMAP24XX_ST_96M_APLL				(1 << 8)

#define OMAP24XX_ST_54M_CLK				(1 << 6)

#define OMAP24XX_ST_12M_CLK				(1 << 5)

#define OMAP24XX_ST_48M_CLK				(1 << 4)

#define OMAP24XX_ST_96M_CLK				(1 << 2)

#define OMAP24XX_ST_54M_APLL_MASK			(1 << 9)

#define OMAP24XX_ST_96M_APLL_MASK			(1 << 8)

#define OMAP24XX_ST_54M_CLK_MASK			(1 << 6)

#define OMAP24XX_ST_12M_CLK_MASK			(1 << 5)

#define OMAP24XX_ST_48M_CLK_MASK			(1 << 4)

#define OMAP24XX_ST_96M_CLK_MASK			(1 << 2)

#define OMAP24XX_ST_CORE_CLK_SHIFT			0

#define OMAP24XX_ST_CORE_CLK_MASK			(0x3 << 0)
@@ -355,11 +355,11 @@ 
#define OMAP24XX_DPLL_DIV_SHIFT				8

#define OMAP24XX_DPLL_DIV_MASK				(0xf << 8)

#define OMAP24XX_54M_SOURCE_SHIFT			5

#define OMAP24XX_54M_SOURCE				(1 << 5)

#define OMAP24XX_54M_SOURCE_MASK			(1 << 5)

#define OMAP2430_96M_SOURCE_SHIFT			4

#define OMAP2430_96M_SOURCE				(1 << 4)

#define OMAP2430_96M_SOURCE_MASK			(1 << 4)

#define OMAP24XX_48M_SOURCE_SHIFT			3

#define OMAP24XX_48M_SOURCE				(1 << 3)

#define OMAP24XX_48M_SOURCE_MASK			(1 << 3)

#define OMAP2430_ALTCLK_SOURCE_SHIFT			0

#define OMAP2430_ALTCLK_SOURCE_MASK			(0x7 << 0)
@@ -369,29 +369,29 @@ 


/* CM_FCLKEN_DSP */

#define OMAP2420_EN_IVA_COP_SHIFT			10

#define OMAP2420_EN_IVA_COP				(1 << 10)

#define OMAP2420_EN_IVA_COP_MASK			(1 << 10)

#define OMAP2420_EN_IVA_MPU_SHIFT			8

#define OMAP2420_EN_IVA_MPU				(1 << 8)

#define OMAP2420_EN_IVA_MPU_MASK			(1 << 8)

#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT		0

#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP			(1 << 0)

#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_MASK		(1 << 0)



/* CM_ICLKEN_DSP */

#define OMAP2420_EN_DSP_IPI_SHIFT			1

#define OMAP2420_EN_DSP_IPI				(1 << 1)

#define OMAP2420_EN_DSP_IPI_MASK			(1 << 1)



/* CM_IDLEST_DSP */

#define OMAP2420_ST_IVA					(1 << 8)

#define OMAP2420_ST_IPI					(1 << 1)

#define OMAP24XX_ST_DSP					(1 << 0)

#define OMAP2420_ST_IVA_MASK				(1 << 8)

#define OMAP2420_ST_IPI_MASK				(1 << 1)

#define OMAP24XX_ST_DSP_MASK				(1 << 0)



/* CM_AUTOIDLE_DSP */

#define OMAP2420_AUTO_DSP_IPI				(1 << 1)

#define OMAP2420_AUTO_DSP_IPI_MASK			(1 << 1)



/* CM_CLKSEL_DSP */

#define OMAP2420_SYNC_IVA				(1 << 13)

#define OMAP2420_SYNC_IVA_MASK				(1 << 13)

#define OMAP2420_CLKSEL_IVA_SHIFT			8

#define OMAP2420_CLKSEL_IVA_MASK			(0x1f << 8)

#define OMAP24XX_SYNC_DSP				(1 << 7)

#define OMAP24XX_SYNC_DSP_MASK				(1 << 7)

#define OMAP24XX_CLKSEL_DSP_IF_SHIFT			5

#define OMAP24XX_CLKSEL_DSP_IF_MASK			(0x3 << 5)

#define OMAP24XX_CLKSEL_DSP_SHIFT			0
@@ -406,24 +406,24 @@ 
/* CM_FCLKEN_MDM */

/* 2430 only */

#define OMAP2430_EN_OSC_SHIFT				1

#define OMAP2430_EN_OSC					(1 << 1)

#define OMAP2430_EN_OSC_MASK				(1 << 1)



/* CM_ICLKEN_MDM */

/* 2430 only */

#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT		0

#define OMAP2430_CM_ICLKEN_MDM_EN_MDM			(1 << 0)

#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_MASK		(1 << 0)



/* CM_IDLEST_MDM specific bits */

/* 2430 only */



/* CM_AUTOIDLE_MDM */

/* 2430 only */

#define OMAP2430_AUTO_OSC				(1 << 1)

#define OMAP2430_AUTO_MDM				(1 << 0)

#define OMAP2430_AUTO_OSC_MASK				(1 << 1)

#define OMAP2430_AUTO_MDM_MASK				(1 << 0)



/* CM_CLKSEL_MDM */

/* 2430 only */

#define OMAP2430_SYNC_MDM				(1 << 4)

#define OMAP2430_SYNC_MDM_MASK				(1 << 4)

#define OMAP2430_CLKSEL_MDM_SHIFT			0

#define OMAP2430_CLKSEL_MDM_MASK			(0xf << 0)

CRA Git | Maintained and supported by SUSTech CRA and CCSE