Commit f382d9eb authored by Archit Taneja's avatar Archit Taneja Committed by Tomi Valkeinen
Browse files

omapdss: HDMI: create a Wrapper library 



HDMI wrapper is a block common to DSS in OMAP4, OMAP5 and DRA7x. Move the
existing functions from ti_hdmi_4xxx_ip.c to a separate file. These funcs are
called directly from the hdmi driver rather than hdmi_ip_ops funtion pointer
calls.

Add new wrapper funcs which can be used by other hdmi libraries like core, pll
and phy. Move some of the enums, structs and funcs related to the wrapper from
ti_hdmi_4xxx_ip.h to ti_hdmi.h. These will be shared amongst the omap4/5 hdmi
platform drivers and other libraries.

The old hdmi_wp_init() is removed since it didn't do anything. Timing parameters
like interlace, hsync_level and vsync_level weren't copied correctly before.
Those are copied correctly now.

The DT/hwmod information for hdmi doesn't split the address space according to
the required sub blocks. Keep the address offset and size information in the
driver for now. This will be removed when the driver gets the information
correctly from DT/hwmod.

Signed-off-by: default avatarArchit Taneja <archit@ti.com>
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
parent 9f192a92

drivers/video/omap2/dss/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -10,5 +10,5 @@ omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o 
omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o

omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o

omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o

omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi.o ti_hdmi_4xxx_ip.o

omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi.o hdmi_wp.o ti_hdmi_4xxx_ip.o

ccflags-$(CONFIG_OMAP2_DSS_DEBUG) += -DDEBUG

drivers/video/omap2/dss/dss_features.c

+0 −5
Original line number Diff line number Diff line
@@ -799,15 +799,10 @@ static const struct ti_hdmi_ip_ops omap4_hdmi_functions = { 
	.read_edid		=	ti_hdmi_4xxx_read_edid,

	.pll_enable		=	ti_hdmi_4xxx_pll_enable,

	.pll_disable		=	ti_hdmi_4xxx_pll_disable,

	.video_enable		=	ti_hdmi_4xxx_wp_video_start,

	.video_disable		=	ti_hdmi_4xxx_wp_video_stop,

	.dump_wrapper		=	ti_hdmi_4xxx_wp_dump,

	.dump_core		=	ti_hdmi_4xxx_core_dump,

	.dump_pll		=	ti_hdmi_4xxx_pll_dump,

	.dump_phy		=	ti_hdmi_4xxx_phy_dump,

#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)

	.audio_enable		=       ti_hdmi_4xxx_wp_audio_enable,

	.audio_disable		=       ti_hdmi_4xxx_wp_audio_disable,

	.audio_start		=       ti_hdmi_4xxx_audio_start,

	.audio_stop		=       ti_hdmi_4xxx_audio_stop,

	.audio_config		=	ti_hdmi_4xxx_audio_config,

drivers/video/omap2/dss/hdmi.c

+10 −16
Original line number Diff line number Diff line
@@ -40,7 +40,6 @@ 
#include "dss.h"

#include "dss_features.h"



#define HDMI_WP			0x0

#define HDMI_CORE_SYS		0x400

#define HDMI_CORE_AV		0x900

#define HDMI_PLLCTRL		0x200
@@ -529,7 +528,7 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev) 


	hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);



	hdmi.ip_data.ops->video_disable(&hdmi.ip_data);

	hdmi_wp_video_stop(&hdmi.ip_data.wp);



	/* config the PLL and PHY hdmi_set_pll_pwrfirst */

	r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
@@ -552,7 +551,7 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev) 
	/* tv size */

	dss_mgr_set_timings(mgr, p);



	r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data);

	r = hdmi_wp_video_start(&hdmi.ip_data.wp);

	if (r)

		goto err_vid_enable;
@@ -563,7 +562,7 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev) 
	return 0;



err_mgr_enable:

	hdmi.ip_data.ops->video_disable(&hdmi.ip_data);

	hdmi_wp_video_stop(&hdmi.ip_data.wp);

err_vid_enable:

	hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);

err_phy_enable:
@@ -579,7 +578,7 @@ static void hdmi_power_off_full(struct omap_dss_device *dssdev) 


	dss_mgr_disable(mgr);



	hdmi.ip_data.ops->video_disable(&hdmi.ip_data);

	hdmi_wp_video_stop(&hdmi.ip_data.wp);

	hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);

	hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
@@ -642,7 +641,7 @@ static void hdmi_dump_regs(struct seq_file *s) 
		return;

	}



	hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s);

	hdmi_wp_dump(&hdmi.ip_data.wp, s);

	hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);

	hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);

	hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
@@ -946,8 +945,7 @@ static int hdmi_audio_enable(struct omap_dss_device *dssdev) 
		goto err;

	}





	r = hdmi.ip_data.ops->audio_enable(&hdmi.ip_data);

	r = hdmi_wp_audio_enable(&hdmi.ip_data.wp, true);

	if (r)

		goto err;
@@ -961,7 +959,7 @@ err: 


static void hdmi_audio_disable(struct omap_dss_device *dssdev)

{

	hdmi.ip_data.ops->audio_disable(&hdmi.ip_data);

	hdmi_wp_audio_enable(&hdmi.ip_data.wp, false);

}



static int hdmi_audio_start(struct omap_dss_device *dssdev)
@@ -1086,7 +1084,6 @@ static void __exit hdmi_uninit_output(struct platform_device *pdev) 
/* HDMI HW IP initialisation */

static int omapdss_hdmihw_probe(struct platform_device *pdev)

{

	struct resource *res;

	int r;



	hdmi.pdev = pdev;
@@ -1094,12 +1091,9 @@ static int omapdss_hdmihw_probe(struct platform_device *pdev) 
	mutex_init(&hdmi.lock);

	mutex_init(&hdmi.ip_data.lock);



	res = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);



	/* Base address taken from platform */

	hdmi.ip_data.base_wp = devm_ioremap_resource(&pdev->dev, res);

	if (IS_ERR(hdmi.ip_data.base_wp))

		return PTR_ERR(hdmi.ip_data.base_wp);

	r = hdmi_wp_init(pdev, &hdmi.ip_data.wp);

	if (r)

		return r;



	hdmi.ip_data.irq = platform_get_irq(pdev, 0);

	if (hdmi.ip_data.irq < 0) {

drivers/video/omap2/dss/hdmi_wp.c

0 → 100644
+302 −0
Original line number Diff line number Diff line 
/*

 * HDMI wrapper

 *

 * Copyright (C) 2013 Texas Instruments Incorporated

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 as published by

 * the Free Software Foundation.

 */



#include <linux/kernel.h>

#include <linux/delay.h>

#include <linux/err.h>

#include <linux/io.h>

#include <linux/platform_device.h>

#include <video/omapdss.h>



#include "dss.h"

#include "ti_hdmi.h"

#include "ti_hdmi_4xxx_ip.h"



static inline void hdmi_write_reg(void __iomem *base_addr, const u16 idx,

		u32 val)

{

	__raw_writel(val, base_addr + idx);

}



static inline u32 hdmi_read_reg(void __iomem *base_addr, const u16 idx)

{

	return __raw_readl(base_addr + idx);

}



#define REG_FLD_MOD(base, idx, val, start, end) \

	hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\

							val, start, end))

#define REG_GET(base, idx, start, end) \

	FLD_GET(hdmi_read_reg(base, idx), start, end)



static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,

		const u16 idx, int b2, int b1, u32 val)

{

	u32 t = 0;

	while (val != REG_GET(base_addr, idx, b2, b1)) {

		udelay(1);

		if (t++ > 10000)

			return !val;

	}

	return val;

}



void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s)

{

#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r))



	DUMPREG(HDMI_WP_REVISION);

	DUMPREG(HDMI_WP_SYSCONFIG);

	DUMPREG(HDMI_WP_IRQSTATUS_RAW);

	DUMPREG(HDMI_WP_IRQSTATUS);

	DUMPREG(HDMI_WP_IRQENABLE_SET);

	DUMPREG(HDMI_WP_IRQENABLE_CLR);

	DUMPREG(HDMI_WP_IRQWAKEEN);

	DUMPREG(HDMI_WP_PWR_CTRL);

	DUMPREG(HDMI_WP_DEBOUNCE);

	DUMPREG(HDMI_WP_VIDEO_CFG);

	DUMPREG(HDMI_WP_VIDEO_SIZE);

	DUMPREG(HDMI_WP_VIDEO_TIMING_H);

	DUMPREG(HDMI_WP_VIDEO_TIMING_V);

	DUMPREG(HDMI_WP_WP_CLK);

	DUMPREG(HDMI_WP_AUDIO_CFG);

	DUMPREG(HDMI_WP_AUDIO_CFG2);

	DUMPREG(HDMI_WP_AUDIO_CTRL);

	DUMPREG(HDMI_WP_AUDIO_DATA);

}



u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp)

{

	return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);

}



void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus)

{

	hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus);

	/* flush posted write */

	hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);

}



void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask)

{

	hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask);

}



void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask)

{

	hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask);

}



/* PHY_PWR_CMD */

int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val)

{

	/* Return if already the state */

	if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val)

		return 0;



	/* Command for power control of HDMI PHY */

	REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6);



	/* Status of the power control of HDMI PHY */

	if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val)

			!= val) {

		pr_err("Failed to set PHY power mode to %d\n", val);

		return -ETIMEDOUT;

	}



	return 0;

}



/* PLL_PWR_CMD */

int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val)

{

	/* Command for power control of HDMI PLL */

	REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2);



	/* wait till PHY_PWR_STATUS is set */

	if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val)

			!= val) {

		pr_err("Failed to set PLL_PWR_STATUS\n");

		return -ETIMEDOUT;

	}



	return 0;

}



int hdmi_wp_video_start(struct hdmi_wp_data *wp)

{

	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31);



	return 0;

}



void hdmi_wp_video_stop(struct hdmi_wp_data *wp)

{

	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31);

}



void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,

		struct hdmi_video_format *video_fmt)

{

	u32 l = 0;



	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode,

		10, 8);



	l |= FLD_VAL(video_fmt->y_res, 31, 16);

	l |= FLD_VAL(video_fmt->x_res, 15, 0);

	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l);

}



void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,

		struct omap_video_timings *timings)

{

	u32 r;

	bool vsync_pol, hsync_pol;

	pr_debug("Enter hdmi_wp_video_config_interface\n");



	vsync_pol = timings->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH;

	hsync_pol = timings->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH;



	r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);

	r = FLD_MOD(r, vsync_pol, 7, 7);

	r = FLD_MOD(r, hsync_pol, 6, 6);

	r = FLD_MOD(r, timings->interlace, 3, 3);

	r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */

	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);

}



void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,

		struct omap_video_timings *timings)

{

	u32 timing_h = 0;

	u32 timing_v = 0;



	pr_debug("Enter hdmi_wp_video_config_timing\n");



	timing_h |= FLD_VAL(timings->hbp, 31, 20);

	timing_h |= FLD_VAL(timings->hfp, 19, 8);

	timing_h |= FLD_VAL(timings->hsw, 7, 0);

	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);



	timing_v |= FLD_VAL(timings->vbp, 31, 20);

	timing_v |= FLD_VAL(timings->vfp, 19, 8);

	timing_v |= FLD_VAL(timings->vsw, 7, 0);

	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v);

}



void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,

		struct omap_video_timings *timings, struct hdmi_config *param)

{

	pr_debug("Enter hdmi_wp_video_init_format\n");



	video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;

	video_fmt->y_res = param->timings.y_res;

	video_fmt->x_res = param->timings.x_res;



	timings->hbp = param->timings.hbp;

	timings->hfp = param->timings.hfp;

	timings->hsw = param->timings.hsw;

	timings->vbp = param->timings.vbp;

	timings->vfp = param->timings.vfp;

	timings->vsw = param->timings.vsw;

	timings->vsync_level = param->timings.vsync_level;

	timings->hsync_level = param->timings.hsync_level;

	timings->interlace = param->timings.interlace;

}



#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)

void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,

		struct hdmi_audio_format *aud_fmt)

{

	u32 r;



	DSSDBG("Enter hdmi_wp_audio_config_format\n");



	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG);

	r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);

	r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);

	r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);

	r = FLD_MOD(r, aud_fmt->type, 4, 4);

	r = FLD_MOD(r, aud_fmt->justification, 3, 3);

	r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);

	r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);

	r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);

	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r);

}



void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,

		struct hdmi_audio_dma *aud_dma)

{

	u32 r;



	DSSDBG("Enter hdmi_wp_audio_config_dma\n");



	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2);

	r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);

	r = FLD_MOD(r, aud_dma->block_size, 7, 0);

	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r);



	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL);

	r = FLD_MOD(r, aud_dma->mode, 9, 9);

	r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);

	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r);

}



int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable)

{

	REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31);



	return 0;

}



int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable)

{

	REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30);



	return 0;

}

#endif



#define WP_SIZE	0x200



int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp)

{

	struct resource *res;

	struct resource temp_res;



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi_wp");

	if (!res) {

		DSSDBG("can't get WP mem resource by name\n");

		/*

		 * if hwmod/DT doesn't have the memory resource information

		 * split into HDMI sub blocks by name, we try again by getting

		 * the platform's first resource. this code will be removed when

		 * the driver can get the mem resources by name

		 */

		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

		if (!res) {

			DSSERR("can't get WP mem resource\n");

			return -EINVAL;

		}



		temp_res.start = res->start;

		temp_res.end = temp_res.start + WP_SIZE - 1;

		res = &temp_res;

	}



	wp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));

	if (!wp->base) {

		DSSERR("can't ioremap HDMI WP\n");

		return -ENOMEM;

	}



	return 0;

}

drivers/video/omap2/dss/ti_hdmi.h

+115 −16
Original line number Diff line number Diff line
@@ -21,6 +21,8 @@ 
#ifndef _TI_HDMI_H

#define _TI_HDMI_H



#include <linux/platform_device.h>



struct hdmi_ip_data;



enum hdmi_pll_pwr {
@@ -30,6 +32,12 @@ enum hdmi_pll_pwr { 
	HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3

};



enum hdmi_phy_pwr {

	HDMI_PHYPWRCMD_OFF = 0,

	HDMI_PHYPWRCMD_LDOON = 1,

	HDMI_PHYPWRCMD_TXON = 2

};



enum hdmi_core_hdmi_dvi {

	HDMI_DVI = 0,

	HDMI_HDMI = 1
@@ -42,11 +50,67 @@ enum hdmi_clk_refsel { 
	HDMI_REFSEL_SYSCLK = 3

};



enum hdmi_packing_mode {

	HDMI_PACK_10b_RGB_YUV444 = 0,

	HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,

	HDMI_PACK_20b_YUV422 = 2,

	HDMI_PACK_ALREADYPACKED = 7

};



enum hdmi_stereo_channels {

	HDMI_AUDIO_STEREO_NOCHANNELS = 0,

	HDMI_AUDIO_STEREO_ONECHANNEL = 1,

	HDMI_AUDIO_STEREO_TWOCHANNELS = 2,

	HDMI_AUDIO_STEREO_THREECHANNELS = 3,

	HDMI_AUDIO_STEREO_FOURCHANNELS = 4

};



enum hdmi_audio_type {

	HDMI_AUDIO_TYPE_LPCM = 0,

	HDMI_AUDIO_TYPE_IEC = 1

};



enum hdmi_audio_justify {

	HDMI_AUDIO_JUSTIFY_LEFT = 0,

	HDMI_AUDIO_JUSTIFY_RIGHT = 1

};



enum hdmi_audio_sample_order {

	HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,

	HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1

};



enum hdmi_audio_samples_perword {

	HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,

	HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1

};



enum hdmi_audio_sample_size {

	HDMI_AUDIO_SAMPLE_16BITS = 0,

	HDMI_AUDIO_SAMPLE_24BITS = 1

};



enum hdmi_audio_transf_mode {

	HDMI_AUDIO_TRANSF_DMA = 0,

	HDMI_AUDIO_TRANSF_IRQ = 1

};



enum hdmi_audio_blk_strt_end_sig {

	HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,

	HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1

};



struct hdmi_cm {

	int	code;

	int	mode;

};



struct hdmi_video_format {

	enum hdmi_packing_mode	packing_mode;

	u32			y_res;	/* Line per panel */

	u32			x_res;	/* pixel per line */

};



struct hdmi_config {

	struct omap_video_timings timings;

	struct hdmi_cm cm;
@@ -63,6 +127,24 @@ struct hdmi_pll_info { 
	enum hdmi_clk_refsel refsel;

};



struct hdmi_audio_format {

	enum hdmi_stereo_channels		stereo_channels;

	u8					active_chnnls_msk;

	enum hdmi_audio_type			type;

	enum hdmi_audio_justify			justification;

	enum hdmi_audio_sample_order		sample_order;

	enum hdmi_audio_samples_perword		samples_per_word;

	enum hdmi_audio_sample_size		sample_size;

	enum hdmi_audio_blk_strt_end_sig	en_sig_blk_strt_end;

};



struct hdmi_audio_dma {

	u8				transfer_size;

	u8				block_size;

	enum hdmi_audio_transf_mode	mode;

	u16				fifo_threshold;

};



struct ti_hdmi_ip_ops {



	void (*video_configure)(struct hdmi_ip_data *ip_data);
@@ -77,12 +159,6 @@ struct ti_hdmi_ip_ops { 


	void (*pll_disable)(struct hdmi_ip_data *ip_data);



	int (*video_enable)(struct hdmi_ip_data *ip_data);



	void (*video_disable)(struct hdmi_ip_data *ip_data);



	void (*dump_wrapper)(struct hdmi_ip_data *ip_data, struct seq_file *s);



	void (*dump_core)(struct hdmi_ip_data *ip_data, struct seq_file *s);



	void (*dump_pll)(struct hdmi_ip_data *ip_data, struct seq_file *s);
@@ -90,10 +166,6 @@ struct ti_hdmi_ip_ops { 
	void (*dump_phy)(struct hdmi_ip_data *ip_data, struct seq_file *s);



#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)

	int (*audio_enable)(struct hdmi_ip_data *ip_data);



	void (*audio_disable)(struct hdmi_ip_data *ip_data);



	int (*audio_start)(struct hdmi_ip_data *ip_data);



	void (*audio_stop)(struct hdmi_ip_data *ip_data);
@@ -147,8 +219,13 @@ struct hdmi_core_infoframe_avi { 
	u16	db12_13_pixel_sofright;

};



struct hdmi_wp_data {

	void __iomem *base;

};



struct hdmi_ip_data {

	void __iomem	*base_wp;	/* HDMI wrapper */

	struct hdmi_wp_data	wp;



	unsigned long	core_sys_offset;

	unsigned long	core_av_offset;

	unsigned long	pll_offset;
@@ -162,22 +239,44 @@ struct hdmi_ip_data { 
	/* ti_hdmi_4xxx_ip private data. These should be in a separate struct */

	struct mutex lock;

};



/* HDMI wrapper funcs */

int hdmi_wp_video_start(struct hdmi_wp_data *wp);

void hdmi_wp_video_stop(struct hdmi_wp_data *wp);

void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);

u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);

void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);

void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);

void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);

int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);

int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);

void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,

		struct hdmi_video_format *video_fmt);

void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,

		struct omap_video_timings *timings);

void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,

		struct omap_video_timings *timings);

void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,

		struct omap_video_timings *timings, struct hdmi_config *param);

int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp);



int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data);

void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data);

int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data, u8 *edid, int len);

int ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data);

void ti_hdmi_4xxx_wp_video_stop(struct hdmi_ip_data *ip_data);

int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data);

void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data);

void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data);

void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);

void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);

void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);

void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);

#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)

int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts);

int ti_hdmi_4xxx_wp_audio_enable(struct hdmi_ip_data *ip_data);

void ti_hdmi_4xxx_wp_audio_disable(struct hdmi_ip_data *ip_data);

int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);

int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);

void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,

		struct hdmi_audio_format *aud_fmt);

void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,

		struct hdmi_audio_dma *aud_dma);

int ti_hdmi_4xxx_audio_start(struct hdmi_ip_data *ip_data);

void ti_hdmi_4xxx_audio_stop(struct hdmi_ip_data *ip_data);

int ti_hdmi_4xxx_audio_config(struct hdmi_ip_data *ip_data,

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