Commit f35b431d authored by Stephen Warren's avatar Stephen Warren Committed by Olof Johansson
Browse files

ARM: tegra: select required CPU and L2 errata options 



The ARM IP revisions in Tegra are:
Tegra20: CPU r1p1, PL310 r2p0
Tegra30: CPU A01=r2p7/>=A02=r2p9, NEON r2p3-50, PL310 r3p1-50

Based on work by Olof Johansson, although the actual list of errata is
somewhat different here, since I added a bunch more and removed one PL310
erratum that doesn't seem applicable.

Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 55256f0e

arch/arm/mach-tegra/Kconfig

+12 −0
Original line number Original line Diff line number Diff line
@@ -10,6 +10,13 @@ config ARCH_TEGRA_2x_SOC 
	select USB_ARCH_HAS_EHCI if USB_SUPPORT

	select USB_ARCH_HAS_EHCI if USB_SUPPORT

	select USB_ULPI if USB_SUPPORT

	select USB_ULPI if USB_SUPPORT

	select USB_ULPI_VIEWPORT if USB_SUPPORT

	select USB_ULPI_VIEWPORT if USB_SUPPORT

	select ARM_ERRATA_720789

	select ARM_ERRATA_742230

	select ARM_ERRATA_751472

	select ARM_ERRATA_754327

	select ARM_ERRATA_764369

	select PL310_ERRATA_727915 if CACHE_L2X0

	select PL310_ERRATA_769419 if CACHE_L2X0

	help

	help

	  Support for NVIDIA Tegra AP20 and T20 processors, based on the

	  Support for NVIDIA Tegra AP20 and T20 processors, based on the

	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller

	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
@@ -23,6 +30,11 @@ config ARCH_TEGRA_3x_SOC 
	select USB_ULPI if USB_SUPPORT

	select USB_ULPI if USB_SUPPORT

	select USB_ULPI_VIEWPORT if USB_SUPPORT

	select USB_ULPI_VIEWPORT if USB_SUPPORT

	select USE_OF

	select USE_OF

	select ARM_ERRATA_743622

	select ARM_ERRATA_751472

	select ARM_ERRATA_754322

	select ARM_ERRATA_764369

	select PL310_ERRATA_769419 if CACHE_L2X0

	help

	help

	  Support for NVIDIA Tegra T30 processor family, based on the

	  Support for NVIDIA Tegra T30 processor family, based on the

	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller

	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller

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