Commit f34dad17 authored by Romain Perier's avatar Romain Perier Committed by Herbert Xu
Browse files

crypto: marvell - Don't break chain for computable last ahash requests 



Currently, the driver breaks chain for all kind of hash requests in order to
don't override intermediate states of partial ahash updates. However, some final
ahash requests can be directly processed by the engine, and so without
intermediate state. This is typically the case for most for the HMAC requests
processed via IPSec.

This commits adds a TDMA descriptor to copy context for these of requests
into the "op" dma pool, then it allow to chain these requests at the DMA level.
The 'complete' operation is also updated to retrieve the MAC digest from the
right location.

Signed-off-by: default avatarRomain Perier <romain.perier@free-electrons.com>
Acked-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 0c99620f

drivers/crypto/marvell/hash.c

+49 −16
Original line number Diff line number Diff line
@@ -312,9 +312,24 @@ static void mv_cesa_ahash_complete(struct crypto_async_request *req) 
	int i;



	digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(ahashreq));



	if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ &&

	    (creq->base.chain.last->flags & CESA_TDMA_TYPE_MSK) == CESA_TDMA_RESULT) {

		__le32 *data = NULL;



		/*

		 * Result is already in the correct endianess when the SA is

		 * used

		 */

		data = creq->base.chain.last->op->ctx.hash.hash;

		for (i = 0; i < digsize / 4; i++)

		creq->state[i] = readl_relaxed(engine->regs + CESA_IVDIG(i));

			creq->state[i] = cpu_to_le32(data[i]);



		memcpy(ahashreq->result, data, digsize);

	} else {

		for (i = 0; i < digsize / 4; i++)

			creq->state[i] = readl_relaxed(engine->regs +

						       CESA_IVDIG(i));

		if (creq->last_req) {

			/*

			* Hardware's MD5 digest is in little endian format, but
@@ -332,6 +347,7 @@ static void mv_cesa_ahash_complete(struct crypto_async_request *req) 
					result[i] = cpu_to_be32(creq->state[i]);

			}

		}

	}



	atomic_sub(ahashreq->nbytes, &engine->load);

}
@@ -504,6 +520,12 @@ mv_cesa_ahash_dma_last_req(struct mv_cesa_tdma_chain *chain, 
						CESA_SA_DESC_CFG_LAST_FRAG,

				      CESA_SA_DESC_CFG_FRAG_MSK);



		ret = mv_cesa_dma_add_result_op(chain,

						CESA_SA_CFG_SRAM_OFFSET,

						CESA_SA_DATA_SRAM_OFFSET,

						CESA_TDMA_SRC_IN_SRAM, flags);

		if (ret)

			return ERR_PTR(-ENOMEM);

		return op;

	}
@@ -564,6 +586,7 @@ static int mv_cesa_ahash_dma_req_init(struct ahash_request *req) 
	struct mv_cesa_op_ctx *op = NULL;

	unsigned int frag_len;

	int ret;

	u32 type;



	basereq->chain.first = NULL;

	basereq->chain.last = NULL;
@@ -635,7 +658,15 @@ static int mv_cesa_ahash_dma_req_init(struct ahash_request *req) 
		goto err_free_tdma;

	}



	if (op) {

	/*

	 * If results are copied via DMA, this means that this

	 * request can be directly processed by the engine,

	 * without partial updates. So we can chain it at the

	 * DMA level with other requests.

	 */

	type = basereq->chain.last->flags & CESA_TDMA_TYPE_MSK;



	if (op && type != CESA_TDMA_RESULT) {

		/* Add dummy desc to wait for crypto operation end */

		ret = mv_cesa_dma_add_dummy_end(&basereq->chain, flags);

		if (ret)
@@ -648,8 +679,10 @@ static int mv_cesa_ahash_dma_req_init(struct ahash_request *req) 
	else

		creq->cache_ptr = 0;



	basereq->chain.last->flags |= (CESA_TDMA_END_OF_REQ |

				       CESA_TDMA_BREAK_CHAIN);

	basereq->chain.last->flags |= CESA_TDMA_END_OF_REQ;



	if (type != CESA_TDMA_RESULT)

		basereq->chain.last->flags |= CESA_TDMA_BREAK_CHAIN;



	return 0;

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