Commit f34b2c26 authored by Yuantian Tang's avatar Yuantian Tang Committed by Stephen Boyd
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dt-bindings: qoriq-clock: add more PLL divider clocks support 



More PLL divider clocks are needed by clock consumer IP. So update
the PLL divider description to make it more general.

Signed-off-by: default avatarYuantian Tang <andy.tang@nxp.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 9e98c678

Documentation/devicetree/bindings/clock/qoriq-clock.txt

+2 −2
Original line number Diff line number Diff line
@@ -83,8 +83,8 @@ second cell is the clock index for the specified type. 
	1	cmux		index (n in CLKCnCSR)

	2	hwaccel		index (n in CLKCGnHWACSR)

	3	fman		0 for fm1, 1 for fm2

	4	platform pll	0=pll, 1=pll/2, 2=pll/3, 3=pll/4

				4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8

	4	platform pll	n=pll/(n+1). For example, when n=1,

				that means output_freq=PLL_freq/2.

	5	coreclk		must be 0



3. Example

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