Commit f34a4c9d authored by Takashi Iwai's avatar Takashi Iwai
Browse files

ALSA: hda: Enable sync-write operation as default for all controllers 

In the end we already enabled the sync-write mode for most of HD-audio
controllers including Intel, and it's no big merit to keep the async
write mode for the rest.  Let's make it as default and drop the
superfluous AZX_DCAPS_SYNC_WRITE bit flag.

Also, avoid to set the allow_bus_reset flag, which is a quite unstable
and hackish behavior that was needed only for some early platforms
(decades ago).  The straight fallback to the single cmd mode is more
robust.

Link: https://lore.kernel.org/r/20200618144051.7415-1-tiwai@suse.de


Signed-off-by: default avatarTakashi Iwai <tiwai@suse.de>
parent c32a5fbc

sound/pci/hda/hda_controller.c

+2 −9
Original line number Diff line number Diff line
@@ -1202,15 +1202,8 @@ int azx_bus_init(struct azx *chip, const char *model) 
	if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY)

		bus->core.align_bdle_4k = true;



	/* AMD chipsets often cause the communication stalls upon certain

	 * sequence like the pin-detection.  It seems that forcing the synced

	 * access works around the stall.  Grrr...

	 */

	if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {

		dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");

	/* enable sync_write flag for stable communication as default */

	bus->core.sync_write = 1;

		bus->allow_bus_reset = 1;

	}



	return 0;

}

sound/pci/hda/hda_controller.h

+1 −1
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ 
#define AZX_DCAPS_POSFIX_LPIB	(1 << 16)	/* Use LPIB as default */

#define AZX_DCAPS_AMD_WORKAROUND (1 << 17)	/* AMD-specific workaround */

#define AZX_DCAPS_NO_64BIT	(1 << 18)	/* No 64bit address */

#define AZX_DCAPS_SYNC_WRITE	(1 << 19)	/* sync each cmd write */

/* 19 unused */

#define AZX_DCAPS_OLD_SSYNC	(1 << 20)	/* Old SSYNC reg for ICH */

#define AZX_DCAPS_NO_ALIGN_BUFSIZE (1 << 21)	/* no buffer size alignment */

/* 22 unused */

sound/pci/hda/hda_intel.c

+7 −9
Original line number Diff line number Diff line
@@ -283,13 +283,12 @@ enum { 


/* quirks for old Intel chipsets */

#define AZX_DCAPS_INTEL_ICH \

	(AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE |\

	 AZX_DCAPS_SYNC_WRITE)

	(AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)



/* quirks for Intel PCH */

#define AZX_DCAPS_INTEL_PCH_BASE \

	(AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\

	 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)

	 AZX_DCAPS_SNOOP_TYPE(SCH))



/* PCH up to IVB; no runtime PM; bind with i915 gfx */

#define AZX_DCAPS_INTEL_PCH_NOPM \
@@ -304,13 +303,13 @@ enum { 
#define AZX_DCAPS_INTEL_HASWELL \

	(/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\

	 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\

	 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)

	 AZX_DCAPS_SNOOP_TYPE(SCH))



/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */

#define AZX_DCAPS_INTEL_BROADWELL \

	(/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\

	 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\

	 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)

	 AZX_DCAPS_SNOOP_TYPE(SCH))



#define AZX_DCAPS_INTEL_BAYTRAIL \

	(AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
@@ -321,19 +320,18 @@ enum { 


#define AZX_DCAPS_INTEL_SKYLAKE \

	(AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\

	 AZX_DCAPS_SYNC_WRITE |\

	 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)



#define AZX_DCAPS_INTEL_BROXTON		AZX_DCAPS_INTEL_SKYLAKE



/* quirks for ATI SB / AMD Hudson */

#define AZX_DCAPS_PRESET_ATI_SB \

	(AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\

	(AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\

	 AZX_DCAPS_SNOOP_TYPE(ATI))



/* quirks for ATI/AMD HDMI */

#define AZX_DCAPS_PRESET_ATI_HDMI \

	(AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\

	(AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\

	 AZX_DCAPS_NO_MSI64)



/* quirks for ATI HDMI with snoop off */
@@ -342,7 +340,7 @@ enum { 


/* quirks for AMD SB */

#define AZX_DCAPS_PRESET_AMD_SB \

	(AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\

	(AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\

	 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)



/* quirks for Nvidia */

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