arm64: cpufeature: Don't enforce system-wide SPE capability (f31deaad) · Commits · 戴 / test

The statistical profiling extension (SPE) is an optional feature of ARMv8.1 and is unlikely to be supported by all of the CPUs in a heterogeneous system. This patch updates the cpufeature checks so that such systems are not tainted as unsupported. Acked-by:

Mark Rutland <mark.rutland@arm.com> Reviewed-by:

Suzuki Poulose <suzuki.poulose@arm.com> Signed-off-by:

Will Deacon <will.deacon@arm.com>

arch/arm64/include/asm/sysreg.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -190,6 +190,7 @@
		#define ID_AA64MMFR2_CNP_SHIFT 0

		/* id_aa64dfr0 */
		#define ID_AA64DFR0_PMSVER_SHIFT 32
		#define ID_AA64DFR0_CTX_CMPS_SHIFT 28
		#define ID_AA64DFR0_WRPS_SHIFT 20
		#define ID_AA64DFR0_BRPS_SHIFT 12

arch/arm64/kernel/cpufeature.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -180,7 +180,8 @@ static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
		};

		static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
		ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
		ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 36, 28, 0),
		ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),

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