Commit f2e04214 authored Feb 09, 2017 by Thomas Gleixner

x86/tsc: Avoid the large time jump when sanitizing TSC ADJUST



Olof reported that on a machine which has a BIOS wreckaged TSC the
timestamps in dmesg are making a large jump because the TSC value is
jumping forward after resetting the TSC ADJUST register to a sane value.

This can be avoided by calling the TSC ADJUST saniziting function before
initializing the per cpu sched clock machinery. That takes the offset into
account and avoid the time jump.

What cannot be avoided is that the 'Firmware Bug' warnings on the secondary
CPUs are printed with the large time offsets because it would be too much
effort and ugly hackery to print those warnings into a buffer and emit them
after the adjustemt on the starting CPUs. It's a firmware bug and should be
fixed in firmware. The weird timestamps are collateral damage and just
illustrate the sillyness of the BIOS folks:

[    0.397445] smp: Bringing up secondary CPUs ...
[    0.402100] x86: Booting SMP configuration:
[    0.406343] .... node  #0, CPUs:      #1
[1265776479.930667] [Firmware Bug]: TSC ADJUST differs: Reference CPU0: -2978888639075328 CPU1: -2978888639183101
[1265776479.944664] TSC ADJUST synchronize: Reference CPU0: 0 CPU1: -2978888639183101
[    0.508119]  #2
[1265776480.032346] [Firmware Bug]: TSC ADJUST differs: Reference CPU0: -2978888639075328 CPU2: -2978888639183677
[1265776480.044192] TSC ADJUST synchronize: Reference CPU0: 0 CPU2: -2978888639183677
[    0.607643]  #3
[1265776480.131874] [Firmware Bug]: TSC ADJUST differs: Reference CPU0: -2978888639075328 CPU3: -2978888639184530
[1265776480.143720] TSC ADJUST synchronize: Reference CPU0: 0 CPU3: -2978888639184530
[    0.707108] smp: Brought up 1 node, 4 CPUs
[    0.711271] smpboot: Total of 4 processors activated (21698.88 BogoMIPS)

Reported-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/20170209151231.411460506@linutronix.de


Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

parent 08b25963

arch/x86/kernel/tsc.c

+3 −2

Original line number	Diff line number	Diff line
		@@ -1356,6 +1356,9 @@ void __init tsc_init(void)
		(unsigned long)cpu_khz / 1000,
		(unsigned long)cpu_khz % 1000);

		/* Sanitize TSC ADJUST before cyc2ns gets initialized */
		tsc_store_and_check_tsc_adjust(true);

		/*
		* Secondary CPUs do not run through tsc_init(), so set up
		* all the scale factors for all CPUs, assuming the same
		@@ -1386,8 +1389,6 @@ void __init tsc_init(void)

		if (unsynchronized_tsc())
		mark_tsc_unstable("TSCs unsynchronized");
		else
		tsc_store_and_check_tsc_adjust(true);

		check_system_tsc_reliable();

Admin message