Commit f2ce6ed3 authored by Carlo Caione's avatar Carlo Caione Committed by Shawn Guo
Browse files

arm64: dts: imx8mq: Fix boot from eMMC 



The boot from eMMC is currently broken on the NXP i.MX8MQ EVK board.
When trying to boot from eMMC it fails with:

...
[    1.271938] mmc1: Tuning failed, falling back to fixed sampling clock
[    1.287429] print_req_error: I/O error, dev mmcblk1, sector 1 flags 0
[    1.306833] mmc1: Tuning failed, falling back to fixed sampling clock
[    1.322325] print_req_error: I/O error, dev mmcblk1, sector 2 flags 0
[    1.329559] Buffer I/O error on dev mmcblk1, logical block 0, async page read
[    1.336714]  mmcblk1: unable to read partition table
...

The problem is the result of a partial misconfiguration of the pins and
the missing assigned clock rate.

Fixes: 9079aca4 ("arm64: add support for i.MX8M EVK board")
Signed-off-by: default avatarCarlo Caione <ccaione@baylibre.com>
Tested-by: default avatarChris Spencer <christopher.spencer@sea.co.uk>
Reviewed-by: default avatarFabio Estevam <festevam@gmail.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent c5b11ee9

arch/arm64/boot/dts/freescale/imx8mq-evk.dts

+22 −22
Original line number Diff line number Diff line
@@ -227,34 +227,34 @@ 


	pinctrl_usdhc1_100mhz: usdhc1-100grp {

		fsl,pins = <

			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x85

			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc5

			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc5

			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc5

			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc5

			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc5

			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc5

			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc5

			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc5

			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc5

			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x85

			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d

			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd

			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd

			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd

			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd

			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd

			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd

			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd

			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd

			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd

			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d

			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1

		>;

	};



	pinctrl_usdhc1_200mhz: usdhc1-200grp {

		fsl,pins = <

			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x87

			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc7

			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc7

			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc7

			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc7

			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc7

			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc7

			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc7

			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc7

			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc7

			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x87

			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f

			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf

			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf

			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf

			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf

			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf

			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf

			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf

			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf

			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf

			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f

			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1

		>;

	};

arch/arm64/boot/dts/freescale/imx8mq.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -360,6 +360,8 @@ 
				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,

				         <&clk IMX8MQ_CLK_USDHC1_ROOT>;

				clock-names = "ipg", "ahb", "per";

				assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;

				assigned-clock-rates = <400000000>;

				fsl,tuning-start-tap = <20>;

				fsl,tuning-step = <2>;

				bus-width = <4>;

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