Commit f2bfc71a authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-fixes-2018-10-18' of... 

Merge tag 'drm-intel-next-fixes-2018-10-18' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

- Fix GPU hang on MacBook2,1 when booting in EFI mode (Bugzilla #105637)
- Fix garbled console on Y tiled BIOS framebuffer configs (Bugzilla #108264)
- Fix black screen on certain eDP panels eg. Dell XPS 9350 (Bugzilla #107489 and #105338)
- MST fixes that Rodrigo dropped from drm-intel-fixes and bunch of Icelake fixes
- Then assorted proactive code fixes caught by CI or developers

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181018165725.GA2281@jlahtine-desk.ger.corp.intel.com
parents c13bbf4a 835fe6d7

drivers/gpu/drm/i915/i915_debugfs.c

+1 −1
Original line number Diff line number Diff line
@@ -4189,7 +4189,7 @@ i915_drop_caches_set(void *data, u64 val) 
						     I915_WAIT_LOCKED,

						     MAX_SCHEDULE_TIMEOUT);



		if (val & DROP_RESET_SEQNO) {

		if (ret == 0 && val & DROP_RESET_SEQNO) {

			intel_runtime_pm_get(i915);

			ret = i915_gem_set_global_seqno(&i915->drm, 1);

			intel_runtime_pm_put(i915);

drivers/gpu/drm/i915/i915_gem.c

+2 −10
Original line number Diff line number Diff line
@@ -1127,11 +1127,7 @@ i915_gem_shmem_pread(struct drm_i915_gem_object *obj, 
	offset = offset_in_page(args->offset);

	for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {

		struct page *page = i915_gem_object_get_page(obj, idx);

		int length;



		length = remain;

		if (offset + length > PAGE_SIZE)

			length = PAGE_SIZE - offset;

		unsigned int length = min_t(u64, remain, PAGE_SIZE - offset);



		ret = shmem_pread(page, offset, length, user_data,

				  page_to_phys(page) & obj_do_bit17_swizzling,
@@ -1575,11 +1571,7 @@ i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj, 
	offset = offset_in_page(args->offset);

	for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {

		struct page *page = i915_gem_object_get_page(obj, idx);

		int length;



		length = remain;

		if (offset + length > PAGE_SIZE)

			length = PAGE_SIZE - offset;

		unsigned int length = min_t(u64, remain, PAGE_SIZE - offset);



		ret = shmem_pwrite(page, offset, length, user_data,

				   page_to_phys(page) & obj_do_bit17_swizzling,

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -9339,6 +9339,9 @@ enum skl_power_gate { 
#define DPCLKA_CFGCR0_ICL			_MMIO(0x164280)

#define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port) ==  PORT_F ? 23 : \

						      (port) + 10))

#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port)   (1 << ((port) + 10))

#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \

						      21 : (tc_port) + 12))

#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port) == PORT_F ? 21 : \

						(port) * 2)

#define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))

drivers/gpu/drm/i915/intel_csr.c

+1 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ 
 */



#define I915_CSR_ICL "i915/icl_dmc_ver1_07.bin"

MODULE_FIRMWARE(I915_CSR_ICL);

#define ICL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 7)



#define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"

drivers/gpu/drm/i915/intel_ddi.c

+26 −10
Original line number Diff line number Diff line
@@ -916,7 +916,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por 
	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;



	if (IS_ICELAKE(dev_priv)) {

		if (port == PORT_A || port == PORT_B)

		if (intel_port_is_combophy(dev_priv, port))

			icl_get_combo_buf_trans(dev_priv, port,

						INTEL_OUTPUT_HDMI, &n_entries);

		else
@@ -1535,7 +1535,7 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder, 
	uint32_t pll_id;



	pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);

	if (port == PORT_A || port == PORT_B) {

	if (intel_port_is_combophy(dev_priv, port)) {

		if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))

			link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);

		else
@@ -2235,7 +2235,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) 
	int n_entries;



	if (IS_ICELAKE(dev_priv)) {

		if (port == PORT_A || port == PORT_B)

		if (intel_port_is_combophy(dev_priv, port))

			icl_get_combo_buf_trans(dev_priv, port, encoder->type,

						&n_entries);

		else
@@ -2669,9 +2669,10 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, 
				    u32 level,

				    enum intel_output_type type)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	enum port port = encoder->port;



	if (port == PORT_A || port == PORT_B)

	if (intel_port_is_combophy(dev_priv, port))

		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);

	else

		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
@@ -2732,6 +2733,21 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp) 
	return DDI_BUF_TRANS_SELECT(level);

}



static inline

uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,

				   enum port port)

{

	if (intel_port_is_combophy(dev_priv, port)) {

		return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);

	} else if (intel_port_is_tc(dev_priv, port)) {

		enum tc_port tc_port = intel_port_to_tc(dev_priv, port);



		return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);

	}



	return 0;

}



void icl_map_plls_to_ports(struct drm_crtc *crtc,

			   struct intel_crtc_state *crtc_state,

			   struct drm_atomic_state *old_state)
@@ -2755,16 +2771,16 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc, 
		mutex_lock(&dev_priv->dpll_lock);



		val = I915_READ(DPCLKA_CFGCR0_ICL);

		WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);

		WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);



		if (port == PORT_A || port == PORT_B) {

		if (intel_port_is_combophy(dev_priv, port)) {

			val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);

			val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);

			I915_WRITE(DPCLKA_CFGCR0_ICL, val);

			POSTING_READ(DPCLKA_CFGCR0_ICL);

		}



		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);

		val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);

		I915_WRITE(DPCLKA_CFGCR0_ICL, val);



		mutex_unlock(&dev_priv->dpll_lock);
@@ -2792,7 +2808,7 @@ void icl_unmap_plls_to_ports(struct drm_crtc *crtc, 
		mutex_lock(&dev_priv->dpll_lock);

		I915_WRITE(DPCLKA_CFGCR0_ICL,

			   I915_READ(DPCLKA_CFGCR0_ICL) |

			   DPCLKA_CFGCR0_DDI_CLK_OFF(port));

			   icl_dpclka_cfgcr0_clk_off(dev_priv, port));

		mutex_unlock(&dev_priv->dpll_lock);

	}

}
@@ -2810,7 +2826,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, 
	mutex_lock(&dev_priv->dpll_lock);



	if (IS_ICELAKE(dev_priv)) {

		if (port >= PORT_C)

		if (!intel_port_is_combophy(dev_priv, port))

			I915_WRITE(DDI_CLK_SEL(port),

				   icl_pll_to_ddi_pll_sel(encoder, pll));

	} else if (IS_CANNONLAKE(dev_priv)) {
@@ -2852,7 +2868,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) 
	enum port port = encoder->port;



	if (IS_ICELAKE(dev_priv)) {

		if (port >= PORT_C)

		if (!intel_port_is_combophy(dev_priv, port))

			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);

	} else if (IS_CANNONLAKE(dev_priv)) {

		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |

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