Commit f2bd8a0e authored by Andrey Grodzovsky's avatar Andrey Grodzovsky Committed by Alex Deucher
Browse files

drm/amdgpu: Fix amdgpu_display_supported_domains logic. 



Add restriction to dissallow GTT domain if the relevant BO
doesn't have USWC flag set to avoid the APU hang scenario.

Signed-off-by: default avatarAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 354e6e14

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

+11 −5
Original line number Diff line number Diff line
@@ -191,7 +191,8 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, 
	}



	if (!adev->enable_virtual_display) {

		r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev));

		r = amdgpu_bo_pin(new_abo,

				  amdgpu_display_supported_domains(adev, new_abo->flags));

		if (unlikely(r != 0)) {

			DRM_ERROR("failed to pin new abo buffer before flip\n");

			goto unreserve;
@@ -495,20 +496,25 @@ static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { 
	.create_handle = drm_gem_fb_create_handle,

};



uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev)

uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,

					  uint64_t bo_flags)

{

	uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;



#if defined(CONFIG_DRM_AMD_DC)

	/*

	 * if amdgpu_bo_validate_uswc returns false it means that USWC mappings

	 * if amdgpu_bo_support_uswc returns false it means that USWC mappings

	 * is not supported for this board. But this mapping is required

	 * to avoid hang caused by placement of scanout BO in GTT on certain

	 * APUs. So force the BO placement to VRAM in case this architecture

	 * will not allow USWC mappings.

	 * Also, don't allow GTT domain if the BO doens't have USWC falg set.

	 */

	if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type <= CHIP_RAVEN &&

	    adev->flags & AMD_IS_APU && amdgpu_bo_support_uswc(0) &&

	if (adev->asic_type >= CHIP_CARRIZO &&

	    adev->asic_type <= CHIP_RAVEN &&

	    (adev->flags & AMD_IS_APU) &&

	    (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&

	    amdgpu_bo_support_uswc(bo_flags) &&

	    amdgpu_device_asic_has_dc_support(adev->asic_type))

		domain |= AMDGPU_GEM_DOMAIN_GTT;

#endif

drivers/gpu/drm/amd/amdgpu/amdgpu_display.h

+2 −1
Original line number Diff line number Diff line
@@ -38,7 +38,8 @@ 
int amdgpu_display_freesync_ioctl(struct drm_device *dev, void *data,

				  struct drm_file *filp);

void amdgpu_display_update_priority(struct amdgpu_device *adev);

uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev);

uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,

					  uint64_t bo_flags);

struct drm_framebuffer *

amdgpu_display_user_framebuffer_create(struct drm_device *dev,

				       struct drm_file *file_priv,

drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c

+1 −1
Original line number Diff line number Diff line
@@ -299,7 +299,7 @@ static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf, 
	struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);

	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);

	struct ttm_operation_ctx ctx = { true, false };

	u32 domain = amdgpu_display_supported_domains(adev);

	u32 domain = amdgpu_display_supported_domains(adev, bo->flags);

	int ret;

	bool reads = (direction == DMA_BIDIRECTIONAL ||

		      direction == DMA_FROM_DEVICE);

drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c

+6 −6
Original line number Diff line number Diff line
@@ -131,6 +131,10 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, 
	int aligned_size, size;

	int height = mode_cmd->height;

	u32 cpp;

	u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |

			       AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS     |

			       AMDGPU_GEM_CREATE_VRAM_CLEARED 	     |

			       AMDGPU_GEM_CREATE_CPU_GTT_USWC;



	info = drm_get_format_info(adev->ddev, mode_cmd);

	cpp = info->cpp[0];
@@ -138,15 +142,11 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, 
	/* need to align pitch with crtc limits */

	mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,

						  fb_tiled);

	domain = amdgpu_display_supported_domains(adev);

	domain = amdgpu_display_supported_domains(adev, flags);

	height = ALIGN(mode_cmd->height, 8);

	size = mode_cmd->pitches[0] * height;

	aligned_size = ALIGN(size, PAGE_SIZE);

	ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain,

				       AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |

				       AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS     |

				       AMDGPU_GEM_CREATE_VRAM_CLEARED 	     |

				       AMDGPU_GEM_CREATE_CPU_GTT_USWC,

	ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain, flags,

				       ttm_bo_type_kernel, NULL, &gobj);

	if (ret) {

		pr_err("failed to allocate framebuffer (%d)\n", aligned_size);

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

+1 −1
Original line number Diff line number Diff line
@@ -765,7 +765,7 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv, 
	args->size = (u64)args->pitch * args->height;

	args->size = ALIGN(args->size, PAGE_SIZE);

	domain = amdgpu_bo_get_preferred_pin_domain(adev,

				amdgpu_display_supported_domains(adev));

				amdgpu_display_supported_domains(adev, flags));

	r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags,

				     ttm_bo_type_device, NULL, &gobj);

	if (r)

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