Commit f2b75bc2 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/pm: correct gfx and pcie settings on umd pstate switching(V2) 



For entering UMD stable Pstate, the operations to enter rlc_safe
mode, disable mgcg_perfmon and disable PCIE aspm are needed. And
the opposite operations should be performed on UMD stable Pstate
exiting.

V2: take those ASICs(CI/SI/VI) which may not support this into
    consideration

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 585584db

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+4 −0
Original line number Diff line number Diff line
@@ -623,6 +623,8 @@ struct amdgpu_asic_funcs { 
	bool (*supports_baco)(struct amdgpu_device *adev);

	/* pre asic_init quirks */

	void (*pre_asic_init)(struct amdgpu_device *adev);

	/* enter/exit umd stable pstate */

	int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);

};



/*
@@ -1165,6 +1167,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev); 
#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))

#define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))

#define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))

#define amdgpu_asic_update_umd_stable_pstate(adev, enter) \

	((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)



#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

+2 −0
Original line number Diff line number Diff line
@@ -1414,6 +1414,7 @@ static int smu_enable_umd_pstate(void *handle, 
							       AMD_CG_STATE_UNGATE);

			smu_gfx_ulv_control(smu, false);

			smu_deep_sleep_control(smu, false);

			amdgpu_asic_update_umd_stable_pstate(smu->adev, true);

		}

	} else {

		/* exit umd pstate, restore level, enable gfx cg*/
@@ -1421,6 +1422,7 @@ static int smu_enable_umd_pstate(void *handle, 
			if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)

				*level = smu_dpm_ctx->saved_dpm_level;

			smu_dpm_ctx->enable_umd_pstate = false;

			amdgpu_asic_update_umd_stable_pstate(smu->adev, false);

			smu_deep_sleep_control(smu, true);

			smu_gfx_ulv_control(smu, true);

			amdgpu_device_ip_set_clockgating_state(smu->adev,

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