Commit f26dbb23 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2019-08-02' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Thanks to Daniel for handling the email the last couple of weeks, flus
  and break-ins combined to derail me. Surprised nothing materialised
  today to take me out again.

  Just more amdgpu navi fixes, msm fixes and a single nouveau regression
  fix:

  amdgpu:
   - navi10 temperature and pstate fixes
   - vcn dynamic power management fix
   - CS ioctl error handling fix
   - debugfs info leak fix
   - amdkfd VegaM fix

  msm:
   - dma sync call fix
   - mdp5 dsi command mode fix
   - fall-through fixes
   - disabled GPU fix

  nouveau:
   - regression fix for displayport MST support"

* tag 'drm-fixes-2019-08-02' of git://anongit.freedesktop.org/drm/drm:
  drm/nouveau: Only release VCPI slots on mode changes
  drm: msm: Fix add_gpu_components
  drm/msm: Annotate intentional switch statement fall throughs
  drm/msm: add support for per-CRTC max_vblank_count on mdp5
  drm/msm: Use the correct dma_sync calls in msm_gem
  drm/amd/powerplay: correct UVD/VCE/VCN power status retrieval
  drm/amd/powerplay: correct Navi10 VCN powergate control (v2)
  drm/amd/powerplay: support VCN powergate status retrieval for SW SMU
  drm/amd/powerplay: support VCN powergate status retrieval on Raven
  drm/amd/powerplay: add new sensor type for VCN powergate status
  drm/amdgpu: fix a potential information leaking bug
  drm/amdgpu: fix error handling in amdgpu_cs_process_fence_dep
  drm/amd/powerplay: enable SW SMU reset functionality
  drm/amd/powerplay: fix null pointer dereference around dpm state relates
  drm/amdgpu/powerplay: use proper revision id for navi
  drm/amd/powerplay: fix temperature granularity error in smu11
  drm/amd/powerplay: add callback function of get_thermal_temperature_range
  drm/amdkfd: Fix byte align on VegaM
parents 42d21900 f8981e03

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

+2 −1
Original line number Diff line number Diff line
@@ -1140,7 +1140,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 
			adev->asic_type != CHIP_FIJI &&

			adev->asic_type != CHIP_POLARIS10 &&

			adev->asic_type != CHIP_POLARIS11 &&

			adev->asic_type != CHIP_POLARIS12) ?

			adev->asic_type != CHIP_POLARIS12 &&

			adev->asic_type != CHIP_VEGAM) ?

			VI_BO_SIZE_ALIGN : 1;



	mapping_flags = AMDGPU_VM_PAGE_READABLE;

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+12 −14
Original line number Diff line number Diff line
@@ -1044,30 +1044,28 @@ static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p, 
			return r;

		}



		fence = amdgpu_ctx_get_fence(ctx, entity,

					     deps[i].handle);

		fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle);

		amdgpu_ctx_put(ctx);



		if (IS_ERR(fence))

			return PTR_ERR(fence);

		else if (!fence)

			continue;



		if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {

			struct drm_sched_fence *s_fence = to_drm_sched_fence(fence);

			struct drm_sched_fence *s_fence;

			struct dma_fence *old = fence;



			s_fence = to_drm_sched_fence(fence);

			fence = dma_fence_get(&s_fence->scheduled);

			dma_fence_put(old);

		}



		if (IS_ERR(fence)) {

			r = PTR_ERR(fence);

			amdgpu_ctx_put(ctx);

			return r;

		} else if (fence) {

			r = amdgpu_sync_fence(p->adev, &p->job->sync, fence,

					true);

		r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);

		dma_fence_put(fence);

			amdgpu_ctx_put(ctx);

		if (r)

			return r;

	}

	}

	return 0;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

+1 −1
Original line number Diff line number Diff line
@@ -707,7 +707,7 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, 
	thread = (*pos & GENMASK_ULL(59, 52)) >> 52;

	bank = (*pos & GENMASK_ULL(61, 60)) >> 60;



	data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);

	data = kcalloc(1024, sizeof(*data), GFP_KERNEL);

	if (!data)

		return -ENOMEM;

drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

+49 −25
Original line number Diff line number Diff line
@@ -159,12 +159,16 @@ static ssize_t amdgpu_get_dpm_state(struct device *dev, 
	struct amdgpu_device *adev = ddev->dev_private;

	enum amd_pm_state_type pm;



	if (is_support_sw_smu(adev) && adev->smu.ppt_funcs->get_current_power_state)

	if (is_support_sw_smu(adev)) {

		if (adev->smu.ppt_funcs->get_current_power_state)

			pm = amdgpu_smu_get_current_power_state(adev);

	else if (adev->powerplay.pp_funcs->get_current_power_state)

		pm = amdgpu_dpm_get_current_power_state(adev);

		else

			pm = adev->pm.dpm.user_state;

	} else if (adev->powerplay.pp_funcs->get_current_power_state) {

		pm = amdgpu_dpm_get_current_power_state(adev);

	} else {

		pm = adev->pm.dpm.user_state;

	}



	return snprintf(buf, PAGE_SIZE, "%s\n",

			(pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
@@ -191,7 +195,11 @@ static ssize_t amdgpu_set_dpm_state(struct device *dev, 
		goto fail;

	}



	if (adev->powerplay.pp_funcs->dispatch_tasks) {

	if (is_support_sw_smu(adev)) {

		mutex_lock(&adev->pm.mutex);

		adev->pm.dpm.user_state = state;

		mutex_unlock(&adev->pm.mutex);

	} else if (adev->powerplay.pp_funcs->dispatch_tasks) {

		amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);

	} else {

		mutex_lock(&adev->pm.mutex);
@@ -3067,6 +3075,21 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a 
	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))

		seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);



	if (adev->asic_type > CHIP_VEGA20) {

		/* VCN clocks */

		if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {

			if (!value) {

				seq_printf(m, "VCN: Disabled\n");

			} else {

				seq_printf(m, "VCN: Enabled\n");

				if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))

					seq_printf(m, "\t%u MHz (DCLK)\n", value/100);

				if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))

					seq_printf(m, "\t%u MHz (VCLK)\n", value/100);

			}

		}

		seq_printf(m, "\n");

	} else {

		/* UVD clocks */

		if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {

			if (!value) {
@@ -3091,6 +3114,7 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a 
					seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);

			}

		}

	}



	return 0;

}

drivers/gpu/drm/amd/include/kgd_pp_interface.h

+1 −0
Original line number Diff line number Diff line
@@ -123,6 +123,7 @@ enum amd_pp_sensors { 
	AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,

	AMDGPU_PP_SENSOR_MIN_FAN_RPM,

	AMDGPU_PP_SENSOR_MAX_FAN_RPM,

	AMDGPU_PP_SENSOR_VCN_POWER_STATE,

};



enum amd_pp_task {

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