Commit f25c42b8 authored by Gevorg Sahakyan's avatar Gevorg Sahakyan Committed by Felipe Balbi
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usb: dwc2: Modify dwc2_readl/writel functions prototype 



Added hsotg argument to dwc2_readl/writel function prototype,
and also instead of address pass offset of register.
hsotg will contain flag field for endianness.

Also customized dwc2_set_bit and dwc2_clear_bit function for
dwc2_readl/writel functions.

Signed-off-by: default avatarGevorg Sahakyan <sahakyan@synopsys.com>
Signed-off-by: default avatarFelipe Balbi <felipe.balbi@linux.intel.com>
parent c31d983b

drivers/usb/dwc2/core.c

+121 −120
Original line number Diff line number Diff line
@@ -73,17 +73,17 @@ int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg) 
	/* Backup global regs */

	gr = &hsotg->gr_backup;



	gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);

	gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK);

	gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);

	gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);

	gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);

	gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);

	gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);

	gr->pcgcctl1 = dwc2_readl(hsotg->regs + PCGCCTL1);

	gr->glpmcfg = dwc2_readl(hsotg->regs + GLPMCFG);

	gr->gi2cctl = dwc2_readl(hsotg->regs + GI2CCTL);

	gr->pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);

	gr->gotgctl = dwc2_readl(hsotg, GOTGCTL);

	gr->gintmsk = dwc2_readl(hsotg, GINTMSK);

	gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG);

	gr->gusbcfg = dwc2_readl(hsotg, GUSBCFG);

	gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ);

	gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);

	gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG);

	gr->pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);

	gr->glpmcfg = dwc2_readl(hsotg, GLPMCFG);

	gr->gi2cctl = dwc2_readl(hsotg, GI2CCTL);

	gr->pcgcctl = dwc2_readl(hsotg, PCGCTL);



	gr->valid = true;

	return 0;
@@ -111,18 +111,18 @@ int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg) 
	}

	gr->valid = false;



	dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);

	dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL);

	dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK);

	dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);

	dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG);

	dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ);

	dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ);

	dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG);

	dwc2_writel(gr->pcgcctl1, hsotg->regs + PCGCCTL1);

	dwc2_writel(gr->glpmcfg, hsotg->regs + GLPMCFG);

	dwc2_writel(gr->pcgcctl, hsotg->regs + PCGCTL);

	dwc2_writel(gr->gi2cctl, hsotg->regs + GI2CCTL);

	dwc2_writel(hsotg, 0xffffffff, GINTSTS);

	dwc2_writel(hsotg, gr->gotgctl, GOTGCTL);

	dwc2_writel(hsotg, gr->gintmsk, GINTMSK);

	dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);

	dwc2_writel(hsotg, gr->gahbcfg, GAHBCFG);

	dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ);

	dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ);

	dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG);

	dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1);

	dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG);

	dwc2_writel(hsotg, gr->pcgcctl, PCGCTL);

	dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL);



	return 0;

}
@@ -141,17 +141,17 @@ int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore) 
	if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL)

		return -ENOTSUPP;



	pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);

	pcgcctl = dwc2_readl(hsotg, PCGCTL);

	pcgcctl &= ~PCGCTL_STOPPCLK;

	dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);

	dwc2_writel(hsotg, pcgcctl, PCGCTL);



	pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);

	pcgcctl = dwc2_readl(hsotg, PCGCTL);

	pcgcctl &= ~PCGCTL_PWRCLMP;

	dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);

	dwc2_writel(hsotg, pcgcctl, PCGCTL);



	pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);

	pcgcctl = dwc2_readl(hsotg, PCGCTL);

	pcgcctl &= ~PCGCTL_RSTPDWNMODULE;

	dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);

	dwc2_writel(hsotg, pcgcctl, PCGCTL);



	udelay(100);

	if (restore) {
@@ -222,21 +222,21 @@ int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg) 
	 * Clear any pending interrupts since dwc2 will not be able to

	 * clear them after entering partial_power_down.

	 */

	dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);

	dwc2_writel(hsotg, 0xffffffff, GINTSTS);



	/* Put the controller in low power state */

	pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);

	pcgcctl = dwc2_readl(hsotg, PCGCTL);



	pcgcctl |= PCGCTL_PWRCLMP;

	dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);

	dwc2_writel(hsotg, pcgcctl, PCGCTL);

	ndelay(20);



	pcgcctl |= PCGCTL_RSTPDWNMODULE;

	dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);

	dwc2_writel(hsotg, pcgcctl, PCGCTL);

	ndelay(20);



	pcgcctl |= PCGCTL_STOPPCLK;

	dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);

	dwc2_writel(hsotg, pcgcctl, PCGCTL);



	return ret;

}
@@ -272,39 +272,39 @@ static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode, 
		if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK))

			pcgcctl |= BIT(17);

	}

	dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);

	dwc2_writel(hsotg, pcgcctl, PCGCTL);



	/* Umnask global Interrupt in GAHBCFG and restore it */

	dwc2_writel(gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG);

	dwc2_writel(hsotg, gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, GAHBCFG);



	/* Clear all pending interupts */

	dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);

	dwc2_writel(hsotg, 0xffffffff, GINTSTS);



	/* Unmask restore done interrupt */

	dwc2_writel(GINTSTS_RESTOREDONE, hsotg->regs + GINTMSK);

	dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTMSK);



	/* Restore GUSBCFG and HCFG/DCFG */

	dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);

	dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);



	if (is_host) {

		dwc2_writel(hr->hcfg, hsotg->regs + HCFG);

		dwc2_writel(hsotg, hr->hcfg, HCFG);

		if (rmode)

			pcgcctl |= PCGCTL_RESTOREMODE;

		dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);

		dwc2_writel(hsotg, pcgcctl, PCGCTL);

		udelay(10);



		pcgcctl |= PCGCTL_ESS_REG_RESTORED;

		dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);

		dwc2_writel(hsotg, pcgcctl, PCGCTL);

		udelay(10);

	} else {

		dwc2_writel(dr->dcfg, hsotg->regs + DCFG);

		dwc2_writel(hsotg, dr->dcfg, DCFG);

		if (!rmode)

			pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE;

		dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);

		dwc2_writel(hsotg, pcgcctl, PCGCTL);

		udelay(10);



		pcgcctl |= PCGCTL_ESS_REG_RESTORED;

		dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);

		dwc2_writel(hsotg, pcgcctl, PCGCTL);

		udelay(10);

	}

}
@@ -322,42 +322,42 @@ void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup, 
	u32 gpwrdn;



	/* Switch-on voltage to the core */

	gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);

	gpwrdn = dwc2_readl(hsotg, GPWRDN);

	gpwrdn &= ~GPWRDN_PWRDNSWTCH;

	dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);

	dwc2_writel(hsotg, gpwrdn, GPWRDN);

	udelay(10);



	/* Reset core */

	gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);

	gpwrdn = dwc2_readl(hsotg, GPWRDN);

	gpwrdn &= ~GPWRDN_PWRDNRSTN;

	dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);

	dwc2_writel(hsotg, gpwrdn, GPWRDN);

	udelay(10);



	/* Enable restore from PMU */

	gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);

	gpwrdn = dwc2_readl(hsotg, GPWRDN);

	gpwrdn |= GPWRDN_RESTORE;

	dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);

	dwc2_writel(hsotg, gpwrdn, GPWRDN);

	udelay(10);



	/* Disable Power Down Clamp */

	gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);

	gpwrdn = dwc2_readl(hsotg, GPWRDN);

	gpwrdn &= ~GPWRDN_PWRDNCLMP;

	dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);

	dwc2_writel(hsotg, gpwrdn, GPWRDN);

	udelay(50);



	if (!is_host && rem_wakeup)

		udelay(70);



	/* Deassert reset core */

	gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);

	gpwrdn = dwc2_readl(hsotg, GPWRDN);

	gpwrdn |= GPWRDN_PWRDNRSTN;

	dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);

	dwc2_writel(hsotg, gpwrdn, GPWRDN);

	udelay(10);



	/* Disable PMU interrupt */

	gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);

	gpwrdn = dwc2_readl(hsotg, GPWRDN);

	gpwrdn &= ~GPWRDN_PMUINTSEL;

	dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);

	dwc2_writel(hsotg, gpwrdn, GPWRDN);

	udelay(10);



	/* Set Restore Essential Regs bit in PCGCCTL register */
@@ -431,7 +431,7 @@ static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg) 
		return false;



	/* Check if core configuration includes the IDDIG filter. */

	ghwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);

	ghwcfg4 = dwc2_readl(hsotg, GHWCFG4);

	if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN))

		return false;
@@ -439,9 +439,9 @@ static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg) 
	 * Check if the IDDIG debounce filter is bypassed. Available

	 * in core version >= 3.10a.

	 */

	gsnpsid = dwc2_readl(hsotg->regs + GSNPSID);

	gsnpsid = dwc2_readl(hsotg, GSNPSID);

	if (gsnpsid >= DWC2_CORE_REV_3_10a) {

		u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);

		u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);



		if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS)

			return false;
@@ -510,8 +510,8 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait) 
	 * reset and account for this delay after the reset.

	 */

	if (dwc2_iddig_filter_enabled(hsotg)) {

		u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);

		u32 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);

		u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);

		u32 gusbcfg = dwc2_readl(hsotg, GUSBCFG);



		if (!(gotgctl & GOTGCTL_CONID_B) ||

		    (gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
@@ -520,9 +520,9 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait) 
	}



	/* Core Soft Reset */

	greset = dwc2_readl(hsotg->regs + GRSTCTL);

	greset = dwc2_readl(hsotg, GRSTCTL);

	greset |= GRSTCTL_CSFTRST;

	dwc2_writel(greset, hsotg->regs + GRSTCTL);

	dwc2_writel(hsotg, greset, GRSTCTL);



	if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_CSFTRST, 50)) {

		dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL GRSTCTL_CSFTRST\n",
@@ -594,14 +594,14 @@ void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host) 
	if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))

		return;



	gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);

	gusbcfg = dwc2_readl(hsotg, GUSBCFG);



	set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;

	clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;



	gusbcfg &= ~clear;

	gusbcfg |= set;

	dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);

	dwc2_writel(hsotg, gusbcfg, GUSBCFG);



	dwc2_wait_for_mode(hsotg, host);

	return;
@@ -627,10 +627,10 @@ static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg) 


	dev_dbg(hsotg->dev, "Clearing force mode bits\n");



	gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);

	gusbcfg = dwc2_readl(hsotg, GUSBCFG);

	gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;

	gusbcfg &= ~GUSBCFG_FORCEDEVMODE;

	dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);

	dwc2_writel(hsotg, gusbcfg, GUSBCFG);



	if (dwc2_iddig_filter_enabled(hsotg))

		msleep(100);
@@ -670,11 +670,11 @@ void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg) 
void dwc2_enable_acg(struct dwc2_hsotg *hsotg)

{

	if (hsotg->params.acg_enable) {

		u32 pcgcctl1 = dwc2_readl(hsotg->regs + PCGCCTL1);

		u32 pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);



		dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n");

		pcgcctl1 |= PCGCCTL1_GATEEN;

		dwc2_writel(pcgcctl1, hsotg->regs + PCGCCTL1);

		dwc2_writel(hsotg, pcgcctl1, PCGCCTL1);

	}

}
@@ -695,56 +695,57 @@ void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg) 
	dev_dbg(hsotg->dev, "Host Global Registers\n");

	addr = hsotg->regs + HCFG;

	dev_dbg(hsotg->dev, "HCFG	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, HCFG));

	addr = hsotg->regs + HFIR;

	dev_dbg(hsotg->dev, "HFIR	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, HFIR));

	addr = hsotg->regs + HFNUM;

	dev_dbg(hsotg->dev, "HFNUM	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, HFNUM));

	addr = hsotg->regs + HPTXSTS;

	dev_dbg(hsotg->dev, "HPTXSTS	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, HPTXSTS));

	addr = hsotg->regs + HAINT;

	dev_dbg(hsotg->dev, "HAINT	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, HAINT));

	addr = hsotg->regs + HAINTMSK;

	dev_dbg(hsotg->dev, "HAINTMSK	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, HAINTMSK));

	if (hsotg->params.dma_desc_enable) {

		addr = hsotg->regs + HFLBADDR;

		dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",

			(unsigned long)addr, dwc2_readl(addr));

			(unsigned long)addr, dwc2_readl(hsotg, HFLBADDR));

	}



	addr = hsotg->regs + HPRT0;

	dev_dbg(hsotg->dev, "HPRT0	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, HPRT0));



	for (i = 0; i < hsotg->params.host_channels; i++) {

		dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);

		addr = hsotg->regs + HCCHAR(i);

		dev_dbg(hsotg->dev, "HCCHAR	 @0x%08lX : 0x%08X\n",

			(unsigned long)addr, dwc2_readl(addr));

			(unsigned long)addr, dwc2_readl(hsotg, HCCHAR(i)));

		addr = hsotg->regs + HCSPLT(i);

		dev_dbg(hsotg->dev, "HCSPLT	 @0x%08lX : 0x%08X\n",

			(unsigned long)addr, dwc2_readl(addr));

			(unsigned long)addr, dwc2_readl(hsotg, HCSPLT(i)));

		addr = hsotg->regs + HCINT(i);

		dev_dbg(hsotg->dev, "HCINT	 @0x%08lX : 0x%08X\n",

			(unsigned long)addr, dwc2_readl(addr));

			(unsigned long)addr, dwc2_readl(hsotg, HCINT(i)));

		addr = hsotg->regs + HCINTMSK(i);

		dev_dbg(hsotg->dev, "HCINTMSK	 @0x%08lX : 0x%08X\n",

			(unsigned long)addr, dwc2_readl(addr));

			(unsigned long)addr, dwc2_readl(hsotg, HCINTMSK(i)));

		addr = hsotg->regs + HCTSIZ(i);

		dev_dbg(hsotg->dev, "HCTSIZ	 @0x%08lX : 0x%08X\n",

			(unsigned long)addr, dwc2_readl(addr));

			(unsigned long)addr, dwc2_readl(hsotg, HCTSIZ(i)));

		addr = hsotg->regs + HCDMA(i);

		dev_dbg(hsotg->dev, "HCDMA	 @0x%08lX : 0x%08X\n",

			(unsigned long)addr, dwc2_readl(addr));

			(unsigned long)addr, dwc2_readl(hsotg, HCDMA(i)));

		if (hsotg->params.dma_desc_enable) {

			addr = hsotg->regs + HCDMAB(i);

			dev_dbg(hsotg->dev, "HCDMAB	 @0x%08lX : 0x%08X\n",

				(unsigned long)addr, dwc2_readl(addr));

				(unsigned long)addr, dwc2_readl(hsotg,

								HCDMAB(i)));

		}

	}

#endif
@@ -766,80 +767,80 @@ void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg) 
	dev_dbg(hsotg->dev, "Core Global Registers\n");

	addr = hsotg->regs + GOTGCTL;

	dev_dbg(hsotg->dev, "GOTGCTL	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GOTGCTL));

	addr = hsotg->regs + GOTGINT;

	dev_dbg(hsotg->dev, "GOTGINT	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GOTGINT));

	addr = hsotg->regs + GAHBCFG;

	dev_dbg(hsotg->dev, "GAHBCFG	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GAHBCFG));

	addr = hsotg->regs + GUSBCFG;

	dev_dbg(hsotg->dev, "GUSBCFG	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GUSBCFG));

	addr = hsotg->regs + GRSTCTL;

	dev_dbg(hsotg->dev, "GRSTCTL	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GRSTCTL));

	addr = hsotg->regs + GINTSTS;

	dev_dbg(hsotg->dev, "GINTSTS	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GINTSTS));

	addr = hsotg->regs + GINTMSK;

	dev_dbg(hsotg->dev, "GINTMSK	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GINTMSK));

	addr = hsotg->regs + GRXSTSR;

	dev_dbg(hsotg->dev, "GRXSTSR	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GRXSTSR));

	addr = hsotg->regs + GRXFSIZ;

	dev_dbg(hsotg->dev, "GRXFSIZ	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GRXFSIZ));

	addr = hsotg->regs + GNPTXFSIZ;

	dev_dbg(hsotg->dev, "GNPTXFSIZ	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GNPTXFSIZ));

	addr = hsotg->regs + GNPTXSTS;

	dev_dbg(hsotg->dev, "GNPTXSTS	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GNPTXSTS));

	addr = hsotg->regs + GI2CCTL;

	dev_dbg(hsotg->dev, "GI2CCTL	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GI2CCTL));

	addr = hsotg->regs + GPVNDCTL;

	dev_dbg(hsotg->dev, "GPVNDCTL	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GPVNDCTL));

	addr = hsotg->regs + GGPIO;

	dev_dbg(hsotg->dev, "GGPIO	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GGPIO));

	addr = hsotg->regs + GUID;

	dev_dbg(hsotg->dev, "GUID	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GUID));

	addr = hsotg->regs + GSNPSID;

	dev_dbg(hsotg->dev, "GSNPSID	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GSNPSID));

	addr = hsotg->regs + GHWCFG1;

	dev_dbg(hsotg->dev, "GHWCFG1	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GHWCFG1));

	addr = hsotg->regs + GHWCFG2;

	dev_dbg(hsotg->dev, "GHWCFG2	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GHWCFG2));

	addr = hsotg->regs + GHWCFG3;

	dev_dbg(hsotg->dev, "GHWCFG3	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GHWCFG3));

	addr = hsotg->regs + GHWCFG4;

	dev_dbg(hsotg->dev, "GHWCFG4	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GHWCFG4));

	addr = hsotg->regs + GLPMCFG;

	dev_dbg(hsotg->dev, "GLPMCFG	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GLPMCFG));

	addr = hsotg->regs + GPWRDN;

	dev_dbg(hsotg->dev, "GPWRDN	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GPWRDN));

	addr = hsotg->regs + GDFIFOCFG;

	dev_dbg(hsotg->dev, "GDFIFOCFG	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, GDFIFOCFG));

	addr = hsotg->regs + HPTXFSIZ;

	dev_dbg(hsotg->dev, "HPTXFSIZ	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, HPTXFSIZ));



	addr = hsotg->regs + PCGCTL;

	dev_dbg(hsotg->dev, "PCGCTL	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

		(unsigned long)addr, dwc2_readl(hsotg, PCGCTL));

#endif

}
@@ -862,7 +863,7 @@ void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num) 


	greset = GRSTCTL_TXFFLSH;

	greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;

	dwc2_writel(greset, hsotg->regs + GRSTCTL);

	dwc2_writel(hsotg, greset, GRSTCTL);



	if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000))

		dev_warn(hsotg->dev, "%s:  HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n",
@@ -889,7 +890,7 @@ void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg) 
			 __func__);



	greset = GRSTCTL_RXFFLSH;

	dwc2_writel(greset, hsotg->regs + GRSTCTL);

	dwc2_writel(hsotg, greset, GRSTCTL);



	/* Wait for RxFIFO flush done */

	if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_RXFFLSH, 10000))
@@ -902,7 +903,7 @@ void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg) 


bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)

{

	if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff)

	if (dwc2_readl(hsotg, GSNPSID) == 0xffffffff)

		return false;

	else

		return true;
@@ -916,10 +917,10 @@ bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) 
 */

void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)

{

	u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);

	u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);



	ahbcfg |= GAHBCFG_GLBL_INTR_EN;

	dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);

	dwc2_writel(hsotg, ahbcfg, GAHBCFG);

}



/**
@@ -930,16 +931,16 @@ void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) 
 */

void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)

{

	u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);

	u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);



	ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;

	dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);

	dwc2_writel(hsotg, ahbcfg, GAHBCFG);

}



/* Returns the controller's GHWCFG2.OTG_MODE. */

unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg)

{

	u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);

	u32 ghwcfg2 = dwc2_readl(hsotg, GHWCFG2);



	return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>

		GHWCFG2_OP_MODE_SHIFT;
@@ -988,7 +989,7 @@ int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask, 
	u32 i;



	for (i = 0; i < timeout; i++) {

		if (dwc2_readl(hsotg->regs + offset) & mask)

		if (dwc2_readl(hsotg, offset) & mask)

			return 0;

		udelay(1);

	}
@@ -1011,7 +1012,7 @@ int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask, 
	u32 i;



	for (i = 0; i < timeout; i++) {

		if (!(dwc2_readl(hsotg->regs + offset) & mask))

		if (!(dwc2_readl(hsotg, offset) & mask))

			return 0;

		udelay(1);

	}

drivers/usb/dwc2/core.h

+13 −12
Original line number Diff line number Diff line
@@ -1172,9 +1172,9 @@ struct dwc2_hsotg { 
 * writes. This set of operations was added specifically for MIPS and

 * should only be used there.

 */

static inline u32 dwc2_readl(const void __iomem *addr)

static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset)

{

	u32 value = __raw_readl(addr);

	u32 value = __raw_readl(hsotg->regs + offset);



	/* In order to preserve endianness __raw_* operation is used. Therefore

	 * a barrier is needed to ensure IO access is not re-ordered across
@@ -1184,9 +1184,9 @@ static inline u32 dwc2_readl(const void __iomem *addr) 
	return value;

}



static inline void dwc2_writel(u32 value, void __iomem *addr)

static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset)

{

	__raw_writel(value, addr);

	__raw_writel(value, hsotg->regs + offset);



	/*

	 * In order to preserve endianness __raw_* operation is used. Therefore
@@ -1195,22 +1195,23 @@ static inline void dwc2_writel(u32 value, void __iomem *addr) 
	 */

	mb();

#ifdef DWC2_LOG_WRITES

	pr_info("INFO:: wrote %08x to %p\n", value, addr);

	pr_info("INFO:: wrote %08x to %p\n", value, hsotg->regs + offset);

#endif

}

#else



/* Normal architectures just use readl/write */

static inline u32 dwc2_readl(const void __iomem *addr)

static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset)

{

	return readl(addr);

	return readl(hsotg->regs + offset);

}



static inline void dwc2_writel(u32 value, void __iomem *addr)

static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset)

{

	writel(value, addr);

	writel(value, hsotg->regs + offset);



#ifdef DWC2_LOG_WRITES

	pr_info("info:: wrote %08x to %p\n", value, addr);

	pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset);

#endif

}

#endif
@@ -1320,12 +1321,12 @@ bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 
 */

static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)

{

	return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0;

	return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0;

}



static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)

{

	return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0;

	return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0;

}



/*

drivers/usb/dwc2/core_intr.c

+59 −59

File changed.

Preview size limit exceeded, changes collapsed.

drivers/usb/dwc2/debugfs.c

+26 −29
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ static int testmode_show(struct seq_file *s, void *unused) 
	int dctl;



	spin_lock_irqsave(&hsotg->lock, flags);

	dctl = dwc2_readl(hsotg->regs + DCTL);

	dctl = dwc2_readl(hsotg, DCTL);

	dctl &= DCTL_TSTCTL_MASK;

	dctl >>= DCTL_TSTCTL_SHIFT;

	spin_unlock_irqrestore(&hsotg->lock, flags);
@@ -126,42 +126,41 @@ static const struct file_operations testmode_fops = { 
static int state_show(struct seq_file *seq, void *v)

{

	struct dwc2_hsotg *hsotg = seq->private;

	void __iomem *regs = hsotg->regs;

	int idx;



	seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",

		   dwc2_readl(regs + DCFG),

		 dwc2_readl(regs + DCTL),

		 dwc2_readl(regs + DSTS));

		   dwc2_readl(hsotg, DCFG),

		 dwc2_readl(hsotg, DCTL),

		 dwc2_readl(hsotg, DSTS));



	seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",

		   dwc2_readl(regs + DIEPMSK), dwc2_readl(regs + DOEPMSK));

		   dwc2_readl(hsotg, DIEPMSK), dwc2_readl(hsotg, DOEPMSK));



	seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",

		   dwc2_readl(regs + GINTMSK),

		   dwc2_readl(regs + GINTSTS));

		   dwc2_readl(hsotg, GINTMSK),

		   dwc2_readl(hsotg, GINTSTS));



	seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",

		   dwc2_readl(regs + DAINTMSK),

		   dwc2_readl(regs + DAINT));

		   dwc2_readl(hsotg, DAINTMSK),

		   dwc2_readl(hsotg, DAINT));



	seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",

		   dwc2_readl(regs + GNPTXSTS),

		   dwc2_readl(regs + GRXSTSR));

		   dwc2_readl(hsotg, GNPTXSTS),

		   dwc2_readl(hsotg, GRXSTSR));



	seq_puts(seq, "\nEndpoint status:\n");



	for (idx = 0; idx < hsotg->num_of_eps; idx++) {

		u32 in, out;



		in = dwc2_readl(regs + DIEPCTL(idx));

		out = dwc2_readl(regs + DOEPCTL(idx));

		in = dwc2_readl(hsotg, DIEPCTL(idx));

		out = dwc2_readl(hsotg, DOEPCTL(idx));



		seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",

			   idx, in, out);



		in = dwc2_readl(regs + DIEPTSIZ(idx));

		out = dwc2_readl(regs + DOEPTSIZ(idx));

		in = dwc2_readl(hsotg, DIEPTSIZ(idx));

		out = dwc2_readl(hsotg, DOEPTSIZ(idx));



		seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",

			   in, out);
@@ -184,14 +183,13 @@ DEFINE_SHOW_ATTRIBUTE(state); 
static int fifo_show(struct seq_file *seq, void *v)

{

	struct dwc2_hsotg *hsotg = seq->private;

	void __iomem *regs = hsotg->regs;

	u32 val;

	int idx;



	seq_puts(seq, "Non-periodic FIFOs:\n");

	seq_printf(seq, "RXFIFO: Size %d\n", dwc2_readl(regs + GRXFSIZ));

	seq_printf(seq, "RXFIFO: Size %d\n", dwc2_readl(hsotg, GRXFSIZ));



	val = dwc2_readl(regs + GNPTXFSIZ);

	val = dwc2_readl(hsotg, GNPTXFSIZ);

	seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",

		   val >> FIFOSIZE_DEPTH_SHIFT,

		   val & FIFOSIZE_STARTADDR_MASK);
@@ -199,7 +197,7 @@ static int fifo_show(struct seq_file *seq, void *v) 
	seq_puts(seq, "\nPeriodic TXFIFOs:\n");



	for (idx = 1; idx < hsotg->num_of_eps; idx++) {

		val = dwc2_readl(regs + DPTXFSIZN(idx));

		val = dwc2_readl(hsotg, DPTXFSIZN(idx));



		seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,

			   val >> FIFOSIZE_DEPTH_SHIFT,
@@ -228,7 +226,6 @@ static int ep_show(struct seq_file *seq, void *v) 
	struct dwc2_hsotg_ep *ep = seq->private;

	struct dwc2_hsotg *hsotg = ep->parent;

	struct dwc2_hsotg_req *req;

	void __iomem *regs = hsotg->regs;

	int index = ep->index;

	int show_limit = 15;

	unsigned long flags;
@@ -239,20 +236,20 @@ static int ep_show(struct seq_file *seq, void *v) 
	/* first show the register state */



	seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",

		   dwc2_readl(regs + DIEPCTL(index)),

		   dwc2_readl(regs + DOEPCTL(index)));

		   dwc2_readl(hsotg, DIEPCTL(index)),

		   dwc2_readl(hsotg, DOEPCTL(index)));



	seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",

		   dwc2_readl(regs + DIEPDMA(index)),

		   dwc2_readl(regs + DOEPDMA(index)));

		   dwc2_readl(hsotg, DIEPDMA(index)),

		   dwc2_readl(hsotg, DOEPDMA(index)));



	seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",

		   dwc2_readl(regs + DIEPINT(index)),

		   dwc2_readl(regs + DOEPINT(index)));

		   dwc2_readl(hsotg, DIEPINT(index)),

		   dwc2_readl(hsotg, DOEPINT(index)));



	seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",

		   dwc2_readl(regs + DIEPTSIZ(index)),

		   dwc2_readl(regs + DOEPTSIZ(index)));

		   dwc2_readl(hsotg, DIEPTSIZ(index)),

		   dwc2_readl(hsotg, DOEPTSIZ(index)));



	seq_puts(seq, "\n");

	seq_printf(seq, "mps %d\n", ep->ep.maxpacket);

drivers/usb/dwc2/gadget.c

+255 −257

File changed.

Preview size limit exceeded, changes collapsed.

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