Commit f23a4704 authored by Kevin Hilman's avatar Kevin Hilman
Browse files

Merge tag 'clk-meson-5.2-1-fixes' of https://github.com/BayLibre/clk-meson into v5.3/dt64 

MPLL50M DT bindings typo fix
Meson9 VPU typo fixes

# gpg: Signature made Tue 11 Jun 2019 05:02:13 AM PDT
# gpg:                using RSA key F4E159AE18F3F56D5F1BB71BE6FC0F1C37F2DA85
# gpg: Good signature from "Jerome Brunet <jbrunet@baylibre.com>" [full]
# gpg:                 aka "Jerome Brunet <jerome@liltaz.com>" [full]
# gpg:                 aka "Jerome Brunet <jerome.brunet@gmail.com>" [full]

* tag 'clk-meson-5.2-1-fixes' of https://github.com/BayLibre/clk-meson:
  clk: meson: meson8b: fix a typo in the VPU parent names array variable
  clk: meson: fix MPLL 50M binding id typo
parents a466a867 3ff46efb

drivers/clk/meson/g12a.c

+2 −2
Original line number Diff line number Diff line
@@ -2734,8 +2734,8 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { 
		[CLKID_MALI_1_DIV]		= &g12a_mali_1_div.hw,

		[CLKID_MALI_1]			= &g12a_mali_1.hw,

		[CLKID_MALI]			= &g12a_mali.hw,

		[CLKID_MPLL_5OM_DIV]		= &g12a_mpll_50m_div.hw,

		[CLKID_MPLL_5OM]		= &g12a_mpll_50m.hw,

		[CLKID_MPLL_50M_DIV]		= &g12a_mpll_50m_div.hw,

		[CLKID_MPLL_50M]		= &g12a_mpll_50m.hw,

		[CLKID_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,

		[CLKID_SYS_PLL_DIV16]		= &g12a_sys_pll_div16.hw,

		[CLKID_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,

drivers/clk/meson/g12a.h

+1 −1
Original line number Diff line number Diff line
@@ -166,7 +166,7 @@ 
#define CLKID_HDMI_DIV				167

#define CLKID_MALI_0_DIV			170

#define CLKID_MALI_1_DIV			173

#define CLKID_MPLL_5OM_DIV			176

#define CLKID_MPLL_50M_DIV			176

#define CLKID_SYS_PLL_DIV16_EN			178

#define CLKID_SYS_PLL_DIV16			179

#define CLKID_CPU_CLK_DYN0_SEL			180

drivers/clk/meson/meson8b.c

+5 −5
Original line number Diff line number Diff line
@@ -1761,7 +1761,7 @@ static struct clk_regmap meson8m2_gp_pll = { 
	},

};



static const char * const mmeson8b_vpu_0_1_parent_names[] = {

static const char * const meson8b_vpu_0_1_parent_names[] = {

	"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"

};
@@ -1778,8 +1778,8 @@ static struct clk_regmap meson8b_vpu_0_sel = { 
	.hw.init = &(struct clk_init_data){

		.name = "vpu_0_sel",

		.ops = &clk_regmap_mux_ops,

		.parent_names = mmeson8b_vpu_0_1_parent_names,

		.num_parents = ARRAY_SIZE(mmeson8b_vpu_0_1_parent_names),

		.parent_names = meson8b_vpu_0_1_parent_names,

		.num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_names),

		.flags = CLK_SET_RATE_PARENT,

	},

};
@@ -1837,8 +1837,8 @@ static struct clk_regmap meson8b_vpu_1_sel = { 
	.hw.init = &(struct clk_init_data){

		.name = "vpu_1_sel",

		.ops = &clk_regmap_mux_ops,

		.parent_names = mmeson8b_vpu_0_1_parent_names,

		.num_parents = ARRAY_SIZE(mmeson8b_vpu_0_1_parent_names),

		.parent_names = meson8b_vpu_0_1_parent_names,

		.num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_names),

		.flags = CLK_SET_RATE_PARENT,

	},

};

include/dt-bindings/clock/g12a-clkc.h

+1 −1
Original line number Diff line number Diff line
@@ -130,7 +130,7 @@ 
#define CLKID_MALI_1_SEL			172

#define CLKID_MALI_1				174

#define CLKID_MALI				175

#define CLKID_MPLL_5OM				177

#define CLKID_MPLL_50M				177

#define CLKID_CPU_CLK				187

#define CLKID_PCIE_PLL				201

#define CLKID_VDEC_1				204

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