ath9k_hw: take care of enabling MCI interrupts (f229f815) · Commits · 戴 / test

enable MCI interrupt when ath9k_hw_enable_interrupts is called, like during the completion of chip_reset before which the interrupts are disabled Cc: Wilson Tsao <wtsao@qca.qualcomm.com> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Signed-off-by:

Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by:

Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by:

John W. Linville <linville@tuxdriver.com>

drivers/net/wireless/ath/ath9k/mac.c

+8 −4

Original line number	Diff line number	Diff line
		@@ -798,6 +798,7 @@ void ath9k_hw_enable_interrupts(struct ath_hw *ah)
		{
		struct ath_common *common = ath9k_hw_common(ah);
		u32 sync_default = AR_INTR_SYNC_DEFAULT;
		u32 async_mask;

		if (!(ah->imask & ATH9K_INT_GLOBAL))
		return;
		@@ -812,13 +813,16 @@ void ath9k_hw_enable_interrupts(struct ath_hw *ah)
		if (AR_SREV_9340(ah))
		sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;

		async_mask = AR_INTR_MAC_IRQ;

		if (ah->imask & ATH9K_INT_MCI)
		async_mask \|= AR_INTR_ASYNC_MASK_MCI;

		ath_dbg(common, ATH_DBG_INTERRUPT, "enable IER\n");
		REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
		if (!AR_SREV_9100(ah)) {
		REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
		AR_INTR_MAC_IRQ);
		REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);

		REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, async_mask);
		REG_WRITE(ah, AR_INTR_ASYNC_MASK, async_mask);

		REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
		REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default);

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