Commit f2131d34 authored by Russell King's avatar Russell King Committed by Russell King
Browse files

[ARM] Always mark ARMv6 PTWs outer cacheable 



Other platforms other than SMP may have an outer cache.  For these, we
also need to mark the page table walks outer cacheable.  Since marking
the walks always outer cacheable apparantly has no side effects, we
might as well always mark them so.

However, we continue to only mark PTWs shared if we have SMP enabled.

Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 3e1a80f1

arch/arm/mm/proc-v6.S

+8 −6
Original line number Diff line number Diff line
@@ -30,6 +30,12 @@ 
#define TTB_RGN_WT	(2 << 3)

#define TTB_RGN_WB	(3 << 3)



#ifndef CONFIG_SMP

#define TTB_FLAGS	TTB_RGN_WBWA

#else

#define TTB_FLAGS	TTB_RGN_WBWA|TTB_S

#endif



ENTRY(cpu_v6_proc_init)

	mov	pc, lr
@@ -92,9 +98,7 @@ ENTRY(cpu_v6_switch_mm) 
#ifdef CONFIG_MMU

	mov	r2, #0

	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id

#ifdef CONFIG_SMP

	orr	r0, r0, #TTB_RGN_WBWA|TTB_S	@ mark PTWs shared, outer cacheable

#endif

	orr	r0, r0, #TTB_FLAGS

	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB

	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer

	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
@@ -204,9 +208,7 @@ __v6_setup: 
#ifdef CONFIG_MMU

	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I + D TLBs

	mcr	p15, 0, r0, c2, c0, 2		@ TTB control register

#ifdef CONFIG_SMP

	orr	r4, r4, #TTB_RGN_WBWA|TTB_S	@ mark PTWs shared, outer cacheable

#endif

	orr	r4, r4, #TTB_FLAGS

	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1

#endif /* CONFIG_MMU */

	adr	r5, v6_crval

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