Commit f1fb60bf authored by Madhavan Srinivasan's avatar Madhavan Srinivasan Committed by Michael Ellerman
Browse files

powerpc/perf: Export Power9 generic and cache events to sysfs 



Export the generic hardware and cache perf events for Power9 to sysfs,
so users can determine the PMU event monitored.

Signed-off-by: default avatarMadhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 8c002dbd

arch/powerpc/perf/power9-pmu.c

+59 −0
Original line number Diff line number Diff line
@@ -31,6 +31,64 @@ enum { 
#define POWER9_MMCRA_IFM2		0x0000000080000000UL

#define POWER9_MMCRA_IFM3		0x00000000C0000000UL



GENERIC_EVENT_ATTR(cpu-cycles,			PM_CYC);

GENERIC_EVENT_ATTR(stalled-cycles-frontend,	PM_ICT_NOSLOT_CYC);

GENERIC_EVENT_ATTR(stalled-cycles-backend,	PM_CMPLU_STALL);

GENERIC_EVENT_ATTR(instructions,		PM_INST_CMPL);

GENERIC_EVENT_ATTR(branch-instructions,		PM_BRU_CMPL);

GENERIC_EVENT_ATTR(branch-misses,		PM_BR_MPRED_CMPL);

GENERIC_EVENT_ATTR(cache-references,		PM_LD_REF_L1);

GENERIC_EVENT_ATTR(cache-misses,		PM_LD_MISS_L1_FIN);



CACHE_EVENT_ATTR(L1-dcache-load-misses,		PM_LD_MISS_L1_FIN);

CACHE_EVENT_ATTR(L1-dcache-loads,		PM_LD_REF_L1);

CACHE_EVENT_ATTR(L1-dcache-prefetches,		PM_L1_PREF);

CACHE_EVENT_ATTR(L1-dcache-store-misses,	PM_ST_MISS_L1);

CACHE_EVENT_ATTR(L1-icache-load-misses,		PM_L1_ICACHE_MISS);

CACHE_EVENT_ATTR(L1-icache-loads,		PM_INST_FROM_L1);

CACHE_EVENT_ATTR(L1-icache-prefetches,		PM_IC_PREF_WRITE);

CACHE_EVENT_ATTR(LLC-load-misses,		PM_DATA_FROM_L3MISS);

CACHE_EVENT_ATTR(LLC-loads,			PM_DATA_FROM_L3);

CACHE_EVENT_ATTR(LLC-prefetches,		PM_L3_PREF_ALL);

CACHE_EVENT_ATTR(LLC-store-misses,		PM_L2_ST_MISS);

CACHE_EVENT_ATTR(LLC-stores,			PM_L2_ST);

CACHE_EVENT_ATTR(branch-load-misses,		PM_BR_MPRED_CMPL);

CACHE_EVENT_ATTR(branch-loads,			PM_BRU_CMPL);

CACHE_EVENT_ATTR(dTLB-load-misses,		PM_DTLB_MISS);

CACHE_EVENT_ATTR(iTLB-load-misses,		PM_ITLB_MISS);



static struct attribute *power9_events_attr[] = {

	GENERIC_EVENT_PTR(PM_CYC),

	GENERIC_EVENT_PTR(PM_ICT_NOSLOT_CYC),

	GENERIC_EVENT_PTR(PM_CMPLU_STALL),

	GENERIC_EVENT_PTR(PM_INST_CMPL),

	GENERIC_EVENT_PTR(PM_BRU_CMPL),

	GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),

	GENERIC_EVENT_PTR(PM_LD_REF_L1),

	GENERIC_EVENT_PTR(PM_LD_MISS_L1_FIN),

	CACHE_EVENT_PTR(PM_LD_MISS_L1_FIN),

	CACHE_EVENT_PTR(PM_LD_REF_L1),

	CACHE_EVENT_PTR(PM_L1_PREF),

	CACHE_EVENT_PTR(PM_ST_MISS_L1),

	CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),

	CACHE_EVENT_PTR(PM_INST_FROM_L1),

	CACHE_EVENT_PTR(PM_IC_PREF_WRITE),

	CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),

	CACHE_EVENT_PTR(PM_DATA_FROM_L3),

	CACHE_EVENT_PTR(PM_L3_PREF_ALL),

	CACHE_EVENT_PTR(PM_L2_ST_MISS),

	CACHE_EVENT_PTR(PM_L2_ST),

	CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),

	CACHE_EVENT_PTR(PM_BRU_CMPL),

	CACHE_EVENT_PTR(PM_DTLB_MISS),

	CACHE_EVENT_PTR(PM_ITLB_MISS),

	NULL

};



static struct attribute_group power9_pmu_events_group = {

	.name = "events",

	.attrs = power9_events_attr,

};



PMU_FORMAT_ATTR(event,		"config:0-49");

PMU_FORMAT_ATTR(pmcxsel,	"config:0-7");
@@ -68,6 +126,7 @@ struct attribute_group power9_pmu_format_group = { 


static const struct attribute_group *power9_pmu_attr_groups[] = {

	&power9_pmu_format_group,

	&power9_pmu_events_group,

	NULL,

};

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