Commit f1f90e25 authored Nov 26, 2018 by Mikulas Patocka Committed by Bjorn Helgaas Nov 30, 2018

PCI: Fix incorrect value returned from pcie_get_speed_cap()

The macros PCI_EXP_LNKCAP_SLS_*GB are values, not bit masks.  We must mask
the register and compare it against them.

This fixes errors like this:

  amdgpu: [powerplay] failed to send message 261 ret is 0

when a PCIe-v3 card is plugged into a PCIe-v1 slot, because the slot is
being incorrectly reported as PCIe-v3 capable.

6cf57be0, which appeared in v4.17, added pcie_get_speed_cap() with the
incorrect test of PCI_EXP_LNKCAP_SLS as a bitmask.  5d9a6330, which
appeared in v4.19, changed amdgpu to use pcie_get_speed_cap(), so the
amdgpu bug reports below are regressions in v4.19.

Fixes: 6cf57be0 ("PCI: Add pcie_get_speed_cap() to find max supported link speed")
Fixes: 5d9a6330 ("drm/amdgpu: use pcie functions for link width and speed")
Link: https://bugs.freedesktop.org/show_bug.cgi?id=108704
Link: https://bugs.freedesktop.org/show_bug.cgi?id=108778


Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
[bhelgaas: update comment, remove use of PCI_EXP_LNKCAP_SLS_8_0GB and
PCI_EXP_LNKCAP_SLS_16_0GB since those should be covered by PCI_EXP_LNKCAP2,
remove test of PCI_EXP_LNKCAP for zero, since that register is required]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org	# v4.17+

parent 0d76bcc9

drivers/pci/pci.c

+11 −13

Original line number	Diff line number	Diff line
		@@ -5556,9 +5556,13 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
		u32 lnkcap2, lnkcap;

		/*
		* PCIe r4.0 sec 7.5.3.18 recommends using the Supported Link
		* Speeds Vector in Link Capabilities 2 when supported, falling
		* back to Max Link Speed in Link Capabilities otherwise.
		* Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
		* implementation note there recommends using the Supported Link
		* Speeds Vector in Link Capabilities 2 when supported.
		*
		* Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
		* should use the Supported Link Speeds field in Link Capabilities,
		* where only 2.5 GT/s and 5.0 GT/s speeds were defined.
		*/
		pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
		if (lnkcap2) { /* PCIe r3.0-compliant */
		@@ -5574,16 +5578,10 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
		}

		pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
		if (lnkcap) {
		if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
		return PCIE_SPEED_16_0GT;
		else if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
		return PCIE_SPEED_8_0GT;
		else if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
		if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
		return PCIE_SPEED_5_0GT;
		else if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
		else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
		return PCIE_SPEED_2_5GT;
		}

		return PCI_SPEED_UNKNOWN;
		}

Admin message