ARM64: dts: marvell: armada-cp110: Add registers clock for XOR engine nodes (f1ebfab9) · Commits · 戴 / test

This extra clock is needed to access the registers of the XOR engine controller used on CP110 component of the Armada 7K/8K SoCs. This follow the changes already made in the binding documentation (as well as in the driver): "dmaengine: mv_xor_v2: Fix clock resource by adding a register clock" Signed-off-by:

Gregory CLEMENT <gregory.clement@bootlin.com>

arch/arm64/boot/dts/marvell/armada-cp110.dtsi

+6 −2

Original line number	Diff line number	Diff line
		@@ -244,7 +244,9 @@
		reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
		dma-coherent;
		msi-parent = <&gic_v2m0>;
		clocks = <&CP110_LABEL(clk) 1 8>;
		clock-names = "core", "reg";
		clocks = <&CP110_LABEL(clk) 1 8>,
		<&CP110_LABEL(clk) 1 14>;
		};

		CP110_LABEL(xor1): xor@6c0000 {
		@@ -252,7 +254,9 @@
		reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
		dma-coherent;
		msi-parent = <&gic_v2m0>;
		clocks = <&CP110_LABEL(clk) 1 7>;
		clock-names = "core", "reg";
		clocks = <&CP110_LABEL(clk) 1 7>,
		<&CP110_LABEL(clk) 1 14>;
		};

		CP110_LABEL(spi0): spi@700600 {

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