Commit f1cc6acf authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Chris Wilson
Browse files

drm/i915/selftests: Add context batchbuffers registers to live_lrc_fixed 



Add per ctx bb and indirect ctx bb register locations to live_lrc_fixed
for verification.

Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200423224159.22078-1-chris@chris-wilson.co.uk
parent cbfd3a0c

drivers/gpu/drm/i915/gt/intel_lrc.c

+73 −55
Original line number Diff line number Diff line
@@ -238,6 +238,70 @@ __execlists_update_reg_state(const struct intel_context *ce, 
			     const struct intel_engine_cs *engine,

			     u32 head);



static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)

{

	if (INTEL_GEN(engine->i915) >= 12)

		return 0x60;

	else if (INTEL_GEN(engine->i915) >= 9)

		return 0x54;

	else if (engine->class == RENDER_CLASS)

		return 0x58;

	else

		return -1;

}



static int lrc_ring_wa_bb_per_ctx(const struct intel_engine_cs *engine)

{

	if (INTEL_GEN(engine->i915) >= 12)

		return 0x12;

	else if (INTEL_GEN(engine->i915) >= 9 || engine->class == RENDER_CLASS)

		return 0x18;

	else

		return -1;

}



static int lrc_ring_indirect_ptr(const struct intel_engine_cs *engine)

{

	int x;



	x = lrc_ring_wa_bb_per_ctx(engine);

	if (x < 0)

		return x;



	return x + 2;

}



static int lrc_ring_indirect_offset(const struct intel_engine_cs *engine)

{

	int x;



	x = lrc_ring_indirect_ptr(engine);

	if (x < 0)

		return x;



	return x + 2;

}



static u32

lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine)

{

	switch (INTEL_GEN(engine->i915)) {

	default:

		MISSING_CASE(INTEL_GEN(engine->i915));

		fallthrough;

	case 12:

		return GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;

	case 11:

		return GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;

	case 10:

		return GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;

	case 9:

		return GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;

	case 8:

		return GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;

	}

}



static u32 intel_context_get_runtime(const struct intel_context *ce)

{

	/*
@@ -1102,18 +1166,6 @@ static void intel_engine_context_out(struct intel_engine_cs *engine) 
	write_sequnlock_irqrestore(&engine->stats.lock, flags);

}



static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)

{

	if (INTEL_GEN(engine->i915) >= 12)

		return 0x60;

	else if (INTEL_GEN(engine->i915) >= 9)

		return 0x54;

	else if (engine->class == RENDER_CLASS)

		return 0x58;

	else

		return -1;

}



static void

execlists_check_context(const struct intel_context *ce,

			const struct intel_engine_cs *engine)
@@ -4673,39 +4725,6 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine) 
	return 0;

}



static u32 intel_lr_indirect_ctx_offset(const struct intel_engine_cs *engine)

{

	u32 indirect_ctx_offset;



	switch (INTEL_GEN(engine->i915)) {

	default:

		MISSING_CASE(INTEL_GEN(engine->i915));

		/* fall through */

	case 12:

		indirect_ctx_offset =

			GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;

		break;

	case 11:

		indirect_ctx_offset =

			GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;

		break;

	case 10:

		indirect_ctx_offset =

			GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;

		break;

	case 9:

		indirect_ctx_offset =

			GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;

		break;

	case 8:

		indirect_ctx_offset =

			GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;

		break;

	}



	return indirect_ctx_offset;

}





static void init_common_reg_state(u32 * const regs,

				  const struct intel_engine_cs *engine,
@@ -4728,27 +4747,29 @@ static void init_common_reg_state(u32 * const regs, 
}



static void init_wa_bb_reg_state(u32 * const regs,

				 const struct intel_engine_cs *engine,

				 u32 pos_bb_per_ctx)

				 const struct intel_engine_cs *engine)

{

	const struct i915_ctx_workarounds * const wa_ctx = &engine->wa_ctx;



	if (wa_ctx->per_ctx.size) {

		const u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);



		regs[pos_bb_per_ctx] =

		GEM_BUG_ON(lrc_ring_wa_bb_per_ctx(engine) == -1);

		regs[lrc_ring_wa_bb_per_ctx(engine) + 1] =

			(ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;

	}



	if (wa_ctx->indirect_ctx.size) {

		const u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);



		regs[pos_bb_per_ctx + 2] =

		GEM_BUG_ON(lrc_ring_indirect_ptr(engine) == -1);

		regs[lrc_ring_indirect_ptr(engine) + 1] =

			(ggtt_offset + wa_ctx->indirect_ctx.offset) |

			(wa_ctx->indirect_ctx.size / CACHELINE_BYTES);



		regs[pos_bb_per_ctx + 4] =

			intel_lr_indirect_ctx_offset(engine) << 6;

		GEM_BUG_ON(lrc_ring_indirect_offset(engine) == -1);

		regs[lrc_ring_indirect_offset(engine) + 1] =

			lrc_ring_indirect_offset_default(engine) << 6;

	}

}
@@ -4797,10 +4818,7 @@ static void execlists_init_reg_state(u32 *regs, 
	init_common_reg_state(regs, engine, ring, inhibit);

	init_ppgtt_reg_state(regs, vm_alias(ce->vm));



	init_wa_bb_reg_state(regs, engine,

			     INTEL_GEN(engine->i915) >= 12 ?

			     GEN12_CTX_BB_PER_CTX_PTR :

			     CTX_BB_PER_CTX_PTR);

	init_wa_bb_reg_state(regs, engine);



	__reset_stop_ring(regs, engine);

}

drivers/gpu/drm/i915/gt/intel_lrc_reg.h

+1 −5
Original line number Diff line number Diff line
@@ -9,14 +9,13 @@ 


#include <linux/types.h>



/* GEN8 to GEN11 Reg State Context */

/* GEN8 to GEN12 Reg State Context */

#define CTX_CONTEXT_CONTROL		(0x02 + 1)

#define CTX_RING_HEAD			(0x04 + 1)

#define CTX_RING_TAIL			(0x06 + 1)

#define CTX_RING_START			(0x08 + 1)

#define CTX_RING_CTL			(0x0a + 1)

#define CTX_BB_STATE			(0x10 + 1)

#define CTX_BB_PER_CTX_PTR		(0x18 + 1)

#define CTX_TIMESTAMP			(0x22 + 1)

#define CTX_PDP3_UDW			(0x24 + 1)

#define CTX_PDP3_LDW			(0x26 + 1)
@@ -30,9 +29,6 @@ 


#define GEN9_CTX_RING_MI_MODE		0x54



/* GEN12+ Reg State Context */

#define GEN12_CTX_BB_PER_CTX_PTR		(0x12 + 1)



#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \

	u32 *reg_state__ = (reg_state); \

	const u64 addr__ = i915_page_dir_dma_addr((ppgtt), (n)); \

drivers/gpu/drm/i915/gt/selftest_lrc.c

+15 −0
Original line number Diff line number Diff line
@@ -4593,6 +4593,21 @@ static int live_lrc_fixed(void *arg) 
				CTX_BB_STATE - 1,

				"BB_STATE"

			},

			{

				i915_mmio_reg_offset(RING_BB_PER_CTX_PTR(engine->mmio_base)),

				lrc_ring_wa_bb_per_ctx(engine),

				"RING_BB_PER_CTX_PTR"

			},

			{

				i915_mmio_reg_offset(RING_INDIRECT_CTX(engine->mmio_base)),

				lrc_ring_indirect_ptr(engine),

				"RING_INDIRECT_CTX_PTR"

			},

			{

				i915_mmio_reg_offset(RING_INDIRECT_CTX_OFFSET(engine->mmio_base)),

				lrc_ring_indirect_offset(engine),

				"RING_INDIRECT_CTX_OFFSET"

			},

			{

				i915_mmio_reg_offset(RING_CTX_TIMESTAMP(engine->mmio_base)),

				CTX_TIMESTAMP - 1,

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