Commit f1cad2ce authored by Jesse Brandeburg's avatar Jesse Brandeburg Committed by Jeff Kirsher
Browse files

iavf: remove references to old names 



Remove the register name references to I40E_VF* and change to
IAVF_VF. Update the descriptor names and defines to the IAVF
name.

Signed-off-by: default avatarJesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 5ec8b7d1

drivers/net/ethernet/intel/iavf/i40e_adminq.c

+14 −14
Original line number Diff line number Diff line
@@ -17,16 +17,16 @@ static void i40e_adminq_init_regs(struct i40e_hw *hw) 
{

	/* set head and tail registers in our local struct */

	if (i40e_is_vf(hw)) {

		hw->aq.asq.tail = I40E_VF_ATQT1;

		hw->aq.asq.head = I40E_VF_ATQH1;

		hw->aq.asq.len  = I40E_VF_ATQLEN1;

		hw->aq.asq.bal  = I40E_VF_ATQBAL1;

		hw->aq.asq.bah  = I40E_VF_ATQBAH1;

		hw->aq.arq.tail = I40E_VF_ARQT1;

		hw->aq.arq.head = I40E_VF_ARQH1;

		hw->aq.arq.len  = I40E_VF_ARQLEN1;

		hw->aq.arq.bal  = I40E_VF_ARQBAL1;

		hw->aq.arq.bah  = I40E_VF_ARQBAH1;

		hw->aq.asq.tail = IAVF_VF_ATQT1;

		hw->aq.asq.head = IAVF_VF_ATQH1;

		hw->aq.asq.len  = IAVF_VF_ATQLEN1;

		hw->aq.asq.bal  = IAVF_VF_ATQBAL1;

		hw->aq.asq.bah  = IAVF_VF_ATQBAH1;

		hw->aq.arq.tail = IAVF_VF_ARQT1;

		hw->aq.arq.head = IAVF_VF_ARQH1;

		hw->aq.arq.len  = IAVF_VF_ARQLEN1;

		hw->aq.arq.bal  = IAVF_VF_ARQBAL1;

		hw->aq.arq.bah  = IAVF_VF_ARQBAH1;

	}

}
@@ -266,7 +266,7 @@ static iavf_status i40e_config_asq_regs(struct i40e_hw *hw) 


	/* set starting point */

	wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |

				  I40E_VF_ATQLEN1_ATQENABLE_MASK));

				  IAVF_VF_ATQLEN1_ATQENABLE_MASK));

	wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa));

	wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa));
@@ -295,7 +295,7 @@ static iavf_status i40e_config_arq_regs(struct i40e_hw *hw) 


	/* set starting point */

	wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |

				  I40E_VF_ARQLEN1_ARQENABLE_MASK));

				  IAVF_VF_ARQLEN1_ARQENABLE_MASK));

	wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa));

	wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa));
@@ -803,7 +803,7 @@ iavf_status iavf_asq_send_command(struct i40e_hw *hw, 
	/* update the error if time out occurred */

	if ((!cmd_completed) &&

	    (!details->async && !details->postpone)) {

		if (rd32(hw, hw->aq.asq.len) & I40E_VF_ATQLEN1_ATQCRIT_MASK) {

		if (rd32(hw, hw->aq.asq.len) & IAVF_VF_ATQLEN1_ATQCRIT_MASK) {

			i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,

				   "AQTX: AQ Critical error.\n");

			status = I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR;
@@ -871,7 +871,7 @@ iavf_status iavf_clean_arq_element(struct i40e_hw *hw, 
	}



	/* set next_to_use to head */

	ntu = rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK;

	ntu = rd32(hw, hw->aq.arq.head) & IAVF_VF_ARQH1_ARQH_MASK;

	if (ntu == ntc) {

		/* nothing to do - shouldn't need to update ring's values */

		ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK;

drivers/net/ethernet/intel/iavf/i40e_common.c

+1 −1
Original line number Diff line number Diff line
@@ -335,7 +335,7 @@ bool iavf_check_asq_alive(struct i40e_hw *hw) 
{

	if (hw->aq.asq.len)

		return !!(rd32(hw, hw->aq.asq.len) &

			  I40E_VF_ATQLEN1_ATQENABLE_MASK);

			  IAVF_VF_ATQLEN1_ATQENABLE_MASK);

	else

		return false;

}

drivers/net/ethernet/intel/iavf/i40e_osdep.h

+1 −1
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ 


#define wr64(a, reg, value)	writeq((value), ((a)->hw_addr + (reg)))

#define rd64(a, reg)		readq((a)->hw_addr + (reg))

#define i40e_flush(a)		readl((a)->hw_addr + I40E_VFGEN_RSTAT)

#define iavf_flush(a)		readl((a)->hw_addr + IAVF_VFGEN_RSTAT)



/* memory allocation tracking */

struct i40e_dma_mem {

drivers/net/ethernet/intel/iavf/i40e_register.h

+64 −64
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* Copyright(c) 2013 - 2018 Intel Corporation. */



#ifndef _I40E_REGISTER_H_

#define _I40E_REGISTER_H_

#ifndef _IAVF_REGISTER_H_

#define _IAVF_REGISTER_H_



#define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */

#define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */

#define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */

#define I40E_VF_ARQH1_ARQH_SHIFT 0

#define I40E_VF_ARQH1_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH1_ARQH_SHIFT)

#define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */

#define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28

#define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQVFE_SHIFT)

#define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29

#define I40E_VF_ARQLEN1_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQOVFL_SHIFT)

#define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30

#define I40E_VF_ARQLEN1_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQCRIT_SHIFT)

#define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31

#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQENABLE_SHIFT)

#define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */

#define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */

#define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */

#define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */

#define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */

#define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28

#define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQVFE_SHIFT)

#define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29

#define I40E_VF_ATQLEN1_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQOVFL_SHIFT)

#define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30

#define I40E_VF_ATQLEN1_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQCRIT_SHIFT)

#define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31

#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQENABLE_SHIFT)

#define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */

#define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */

#define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0

#define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT)

#define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */

#define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0

#define I40E_VFINT_DYN_CTL01_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_SHIFT)

#define I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3

#define I40E_VFINT_DYN_CTL01_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT)

#define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */

#define I40E_VFINT_DYN_CTLN1_INTENA_SHIFT 0

#define I40E_VFINT_DYN_CTLN1_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_SHIFT)

#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2

#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT)

#define I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3

#define I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)

#define I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5

#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24

#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT)

#define I40E_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */

#define I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30

#define I40E_VFINT_ICR0_ENA1_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT)

#define I40E_VFINT_ICR0_ENA1_RSVD_SHIFT 31

#define I40E_VFINT_ICR01 0x00004800 /* Reset: CORER */

#define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */

#define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */

#define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */

#define I40E_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */

#define I40E_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */

#define I40E_VFQF_HKEY_MAX_INDEX 12

#define I40E_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */

#define I40E_VFQF_HLUT_MAX_INDEX 15

#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30

#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT)

#endif /* _I40E_REGISTER_H_ */
 
#define IAVF_VF_ARQBAH1 0x00006000 /* Reset: EMPR */

#define IAVF_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */

#define IAVF_VF_ARQH1 0x00007400 /* Reset: EMPR */

#define IAVF_VF_ARQH1_ARQH_SHIFT 0

#define IAVF_VF_ARQH1_ARQH_MASK IAVF_MASK(0x3FF, IAVF_VF_ARQH1_ARQH_SHIFT)

#define IAVF_VF_ARQLEN1 0x00008000 /* Reset: EMPR */

#define IAVF_VF_ARQLEN1_ARQVFE_SHIFT 28

#define IAVF_VF_ARQLEN1_ARQVFE_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQVFE_SHIFT)

#define IAVF_VF_ARQLEN1_ARQOVFL_SHIFT 29

#define IAVF_VF_ARQLEN1_ARQOVFL_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQOVFL_SHIFT)

#define IAVF_VF_ARQLEN1_ARQCRIT_SHIFT 30

#define IAVF_VF_ARQLEN1_ARQCRIT_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQCRIT_SHIFT)

#define IAVF_VF_ARQLEN1_ARQENABLE_SHIFT 31

#define IAVF_VF_ARQLEN1_ARQENABLE_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQENABLE_SHIFT)

#define IAVF_VF_ARQT1 0x00007000 /* Reset: EMPR */

#define IAVF_VF_ATQBAH1 0x00007800 /* Reset: EMPR */

#define IAVF_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */

#define IAVF_VF_ATQH1 0x00006400 /* Reset: EMPR */

#define IAVF_VF_ATQLEN1 0x00006800 /* Reset: EMPR */

#define IAVF_VF_ATQLEN1_ATQVFE_SHIFT 28

#define IAVF_VF_ATQLEN1_ATQVFE_MASK IAVF_MASK(0x1, IAVF_VF_ATQLEN1_ATQVFE_SHIFT)

#define IAVF_VF_ATQLEN1_ATQOVFL_SHIFT 29

#define IAVF_VF_ATQLEN1_ATQOVFL_MASK IAVF_MASK(0x1, IAVF_VF_ATQLEN1_ATQOVFL_SHIFT)

#define IAVF_VF_ATQLEN1_ATQCRIT_SHIFT 30

#define IAVF_VF_ATQLEN1_ATQCRIT_MASK IAVF_MASK(0x1, IAVF_VF_ATQLEN1_ATQCRIT_SHIFT)

#define IAVF_VF_ATQLEN1_ATQENABLE_SHIFT 31

#define IAVF_VF_ATQLEN1_ATQENABLE_MASK IAVF_MASK(0x1, IAVF_VF_ATQLEN1_ATQENABLE_SHIFT)

#define IAVF_VF_ATQT1 0x00008400 /* Reset: EMPR */

#define IAVF_VFGEN_RSTAT 0x00008800 /* Reset: VFR */

#define IAVF_VFGEN_RSTAT_VFR_STATE_SHIFT 0

#define IAVF_VFGEN_RSTAT_VFR_STATE_MASK IAVF_MASK(0x3, IAVF_VFGEN_RSTAT_VFR_STATE_SHIFT)

#define IAVF_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */

#define IAVF_VFINT_DYN_CTL01_INTENA_SHIFT 0

#define IAVF_VFINT_DYN_CTL01_INTENA_MASK IAVF_MASK(0x1, IAVF_VFINT_DYN_CTL01_INTENA_SHIFT)

#define IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3

#define IAVF_VFINT_DYN_CTL01_ITR_INDX_MASK IAVF_MASK(0x3, IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT)

#define IAVF_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */

#define IAVF_VFINT_DYN_CTLN1_INTENA_SHIFT 0

#define IAVF_VFINT_DYN_CTLN1_INTENA_MASK IAVF_MASK(0x1, IAVF_VFINT_DYN_CTLN1_INTENA_SHIFT)

#define IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2

#define IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_MASK IAVF_MASK(0x1, IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT)

#define IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3

#define IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK IAVF_MASK(0x3, IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)

#define IAVF_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5

#define IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24

#define IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK IAVF_MASK(0x1, IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT)

#define IAVF_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */

#define IAVF_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30

#define IAVF_VFINT_ICR0_ENA1_ADMINQ_MASK IAVF_MASK(0x1, IAVF_VFINT_ICR0_ENA1_ADMINQ_SHIFT)

#define IAVF_VFINT_ICR0_ENA1_RSVD_SHIFT 31

#define IAVF_VFINT_ICR01 0x00004800 /* Reset: CORER */

#define IAVF_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */

#define IAVF_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */

#define IAVF_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */

#define IAVF_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */

#define IAVF_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */

#define IAVF_VFQF_HKEY_MAX_INDEX 12

#define IAVF_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */

#define IAVF_VFQF_HLUT_MAX_INDEX 15

#define IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30

#define IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK IAVF_MASK(0x1, IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT)

#endif /* _IAVF_REGISTER_H_ */

drivers/net/ethernet/intel/iavf/i40e_type.h

+87 −87
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ 
#define I40E_RXQ_CTX_DBUFF_SHIFT 7



/* I40E_MASK is a macro used on 32 bit registers */

#define I40E_MASK(mask, shift) ((u32)(mask) << (shift))

#define IAVF_MASK(mask, shift) ((u32)(mask) << (shift))



#define I40E_MAX_VSI_QP			16

#define I40E_MAX_VF_VSI			3
@@ -286,45 +286,45 @@ union i40e_32byte_rx_desc { 


enum i40e_rx_desc_status_bits {

	/* Note: These are predefined bit offsets */

	I40E_RX_DESC_STATUS_DD_SHIFT		= 0,

	I40E_RX_DESC_STATUS_EOF_SHIFT		= 1,

	I40E_RX_DESC_STATUS_L2TAG1P_SHIFT	= 2,

	I40E_RX_DESC_STATUS_L3L4P_SHIFT		= 3,

	I40E_RX_DESC_STATUS_CRCP_SHIFT		= 4,

	I40E_RX_DESC_STATUS_TSYNINDX_SHIFT	= 5, /* 2 BITS */

	I40E_RX_DESC_STATUS_TSYNVALID_SHIFT	= 7,

	IAVF_RX_DESC_STATUS_DD_SHIFT		= 0,

	IAVF_RX_DESC_STATUS_EOF_SHIFT		= 1,

	IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT	= 2,

	IAVF_RX_DESC_STATUS_L3L4P_SHIFT		= 3,

	IAVF_RX_DESC_STATUS_CRCP_SHIFT		= 4,

	IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT	= 5, /* 2 BITS */

	IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT	= 7,

	/* Note: Bit 8 is reserved in X710 and XL710 */

	I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT	= 8,

	I40E_RX_DESC_STATUS_UMBCAST_SHIFT	= 9, /* 2 BITS */

	I40E_RX_DESC_STATUS_FLM_SHIFT		= 11,

	I40E_RX_DESC_STATUS_FLTSTAT_SHIFT	= 12, /* 2 BITS */

	I40E_RX_DESC_STATUS_LPBK_SHIFT		= 14,

	I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT	= 15,

	I40E_RX_DESC_STATUS_RESERVED_SHIFT	= 16, /* 2 BITS */

	IAVF_RX_DESC_STATUS_EXT_UDP_0_SHIFT	= 8,

	IAVF_RX_DESC_STATUS_UMBCAST_SHIFT	= 9, /* 2 BITS */

	IAVF_RX_DESC_STATUS_FLM_SHIFT		= 11,

	IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT	= 12, /* 2 BITS */

	IAVF_RX_DESC_STATUS_LPBK_SHIFT		= 14,

	IAVF_RX_DESC_STATUS_IPV6EXADD_SHIFT	= 15,

	IAVF_RX_DESC_STATUS_RESERVED_SHIFT	= 16, /* 2 BITS */

	/* Note: For non-tunnel packets INT_UDP_0 is the right status for

	 * UDP header

	 */

	I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT	= 18,

	I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */

	IAVF_RX_DESC_STATUS_INT_UDP_0_SHIFT	= 18,

	IAVF_RX_DESC_STATUS_LAST /* this entry must be last!!! */

};



#define I40E_RXD_QW1_STATUS_SHIFT	0

#define I40E_RXD_QW1_STATUS_MASK	((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \

#define I40E_RXD_QW1_STATUS_MASK	((BIT(IAVF_RX_DESC_STATUS_LAST) - 1) \

					 << I40E_RXD_QW1_STATUS_SHIFT)



#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT

#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT

#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK  (0x3UL << \

					    I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)



#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT

#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT

#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \

				    BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)



enum i40e_rx_desc_fltstat_values {

	I40E_RX_DESC_FLTSTAT_NO_DATA	= 0,

	I40E_RX_DESC_FLTSTAT_RSV_FD_ID	= 1, /* 16byte desc? FD_ID : RSV */

	I40E_RX_DESC_FLTSTAT_RSV	= 2,

	I40E_RX_DESC_FLTSTAT_RSS_HASH	= 3,

	IAVF_RX_DESC_FLTSTAT_NO_DATA	= 0,

	IAVF_RX_DESC_FLTSTAT_RSV_FD_ID	= 1, /* 16byte desc? FD_ID : RSV */

	IAVF_RX_DESC_FLTSTAT_RSV	= 2,

	IAVF_RX_DESC_FLTSTAT_RSS_HASH	= 3,

};



#define I40E_RXD_QW1_ERROR_SHIFT	19
@@ -332,23 +332,23 @@ enum i40e_rx_desc_fltstat_values { 


enum i40e_rx_desc_error_bits {

	/* Note: These are predefined bit offsets */

	I40E_RX_DESC_ERROR_RXE_SHIFT		= 0,

	I40E_RX_DESC_ERROR_RECIPE_SHIFT		= 1,

	I40E_RX_DESC_ERROR_HBO_SHIFT		= 2,

	I40E_RX_DESC_ERROR_L3L4E_SHIFT		= 3, /* 3 BITS */

	I40E_RX_DESC_ERROR_IPE_SHIFT		= 3,

	I40E_RX_DESC_ERROR_L4E_SHIFT		= 4,

	I40E_RX_DESC_ERROR_EIPE_SHIFT		= 5,

	I40E_RX_DESC_ERROR_OVERSIZE_SHIFT	= 6,

	I40E_RX_DESC_ERROR_PPRS_SHIFT		= 7

	IAVF_RX_DESC_ERROR_RXE_SHIFT		= 0,

	IAVF_RX_DESC_ERROR_RECIPE_SHIFT		= 1,

	IAVF_RX_DESC_ERROR_HBO_SHIFT		= 2,

	IAVF_RX_DESC_ERROR_L3L4E_SHIFT		= 3, /* 3 BITS */

	IAVF_RX_DESC_ERROR_IPE_SHIFT		= 3,

	IAVF_RX_DESC_ERROR_L4E_SHIFT		= 4,

	IAVF_RX_DESC_ERROR_EIPE_SHIFT		= 5,

	IAVF_RX_DESC_ERROR_OVERSIZE_SHIFT	= 6,

	IAVF_RX_DESC_ERROR_PPRS_SHIFT		= 7

};



enum i40e_rx_desc_error_l3l4e_fcoe_masks {

	I40E_RX_DESC_ERROR_L3L4E_NONE		= 0,

	I40E_RX_DESC_ERROR_L3L4E_PROT		= 1,

	I40E_RX_DESC_ERROR_L3L4E_FC		= 2,

	I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR	= 3,

	I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN	= 4

	IAVF_RX_DESC_ERROR_L3L4E_NONE		= 0,

	IAVF_RX_DESC_ERROR_L3L4E_PROT		= 1,

	IAVF_RX_DESC_ERROR_L3L4E_FC		= 2,

	IAVF_RX_DESC_ERROR_L3L4E_DMAC_ERR	= 3,

	IAVF_RX_DESC_ERROR_L3L4E_DMAC_WARN	= 4

};



#define I40E_RXD_QW1_PTYPE_SHIFT	30
@@ -456,26 +456,26 @@ enum i40e_rx_ptype_payload_layer { 


enum i40e_rx_desc_ext_status_bits {

	/* Note: These are predefined bit offsets */

	I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT	= 0,

	I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT	= 1,

	I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT	= 2, /* 2 BITS */

	I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT	= 4, /* 2 BITS */

	I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT	= 9,

	I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT	= 10,

	I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT	= 11,

	IAVF_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT	= 0,

	IAVF_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT	= 1,

	IAVF_RX_DESC_EXT_STATUS_FLEXBL_SHIFT	= 2, /* 2 BITS */

	IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT	= 4, /* 2 BITS */

	IAVF_RX_DESC_EXT_STATUS_FDLONGB_SHIFT	= 9,

	IAVF_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT	= 10,

	IAVF_RX_DESC_EXT_STATUS_PELONGB_SHIFT	= 11,

};



enum i40e_rx_desc_pe_status_bits {

	/* Note: These are predefined bit offsets */

	I40E_RX_DESC_PE_STATUS_QPID_SHIFT	= 0, /* 18 BITS */

	I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT	= 0, /* 16 BITS */

	I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT	= 16, /* 8 BITS */

	I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT	= 24,

	I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT	= 25,

	I40E_RX_DESC_PE_STATUS_PORTV_SHIFT	= 26,

	I40E_RX_DESC_PE_STATUS_URG_SHIFT	= 27,

	I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT	= 28,

	I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT	= 29

	IAVF_RX_DESC_PE_STATUS_QPID_SHIFT	= 0, /* 18 BITS */

	IAVF_RX_DESC_PE_STATUS_L4PORT_SHIFT	= 0, /* 16 BITS */

	IAVF_RX_DESC_PE_STATUS_IPINDEX_SHIFT	= 16, /* 8 BITS */

	IAVF_RX_DESC_PE_STATUS_QPIDHIT_SHIFT	= 24,

	IAVF_RX_DESC_PE_STATUS_APBVTHIT_SHIFT	= 25,

	IAVF_RX_DESC_PE_STATUS_PORTV_SHIFT	= 26,

	IAVF_RX_DESC_PE_STATUS_URG_SHIFT	= 27,

	IAVF_RX_DESC_PE_STATUS_IPFRAG_SHIFT	= 28,

	IAVF_RX_DESC_PE_STATUS_IPOPT_SHIFT	= 29

};



#define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT		38
@@ -519,40 +519,40 @@ struct i40e_tx_desc { 
#define I40E_TXD_QW1_DTYPE_MASK		(0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)



enum i40e_tx_desc_dtype_value {

	I40E_TX_DESC_DTYPE_DATA		= 0x0,

	I40E_TX_DESC_DTYPE_NOP		= 0x1, /* same as Context desc */

	I40E_TX_DESC_DTYPE_CONTEXT	= 0x1,

	I40E_TX_DESC_DTYPE_FCOE_CTX	= 0x2,

	I40E_TX_DESC_DTYPE_FILTER_PROG	= 0x8,

	I40E_TX_DESC_DTYPE_DDP_CTX	= 0x9,

	I40E_TX_DESC_DTYPE_FLEX_DATA	= 0xB,

	I40E_TX_DESC_DTYPE_FLEX_CTX_1	= 0xC,

	I40E_TX_DESC_DTYPE_FLEX_CTX_2	= 0xD,

	I40E_TX_DESC_DTYPE_DESC_DONE	= 0xF

	IAVF_TX_DESC_DTYPE_DATA		= 0x0,

	IAVF_TX_DESC_DTYPE_NOP		= 0x1, /* same as Context desc */

	IAVF_TX_DESC_DTYPE_CONTEXT	= 0x1,

	IAVF_TX_DESC_DTYPE_FCOE_CTX	= 0x2,

	IAVF_TX_DESC_DTYPE_FILTER_PROG	= 0x8,

	IAVF_TX_DESC_DTYPE_DDP_CTX	= 0x9,

	IAVF_TX_DESC_DTYPE_FLEX_DATA	= 0xB,

	IAVF_TX_DESC_DTYPE_FLEX_CTX_1	= 0xC,

	IAVF_TX_DESC_DTYPE_FLEX_CTX_2	= 0xD,

	IAVF_TX_DESC_DTYPE_DESC_DONE	= 0xF

};



#define I40E_TXD_QW1_CMD_SHIFT	4

#define I40E_TXD_QW1_CMD_MASK	(0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)



enum i40e_tx_desc_cmd_bits {

	I40E_TX_DESC_CMD_EOP			= 0x0001,

	I40E_TX_DESC_CMD_RS			= 0x0002,

	I40E_TX_DESC_CMD_ICRC			= 0x0004,

	I40E_TX_DESC_CMD_IL2TAG1		= 0x0008,

	I40E_TX_DESC_CMD_DUMMY			= 0x0010,

	I40E_TX_DESC_CMD_IIPT_NONIP		= 0x0000, /* 2 BITS */

	I40E_TX_DESC_CMD_IIPT_IPV6		= 0x0020, /* 2 BITS */

	I40E_TX_DESC_CMD_IIPT_IPV4		= 0x0040, /* 2 BITS */

	I40E_TX_DESC_CMD_IIPT_IPV4_CSUM		= 0x0060, /* 2 BITS */

	I40E_TX_DESC_CMD_FCOET			= 0x0080,

	I40E_TX_DESC_CMD_L4T_EOFT_UNK		= 0x0000, /* 2 BITS */

	I40E_TX_DESC_CMD_L4T_EOFT_TCP		= 0x0100, /* 2 BITS */

	I40E_TX_DESC_CMD_L4T_EOFT_SCTP		= 0x0200, /* 2 BITS */

	I40E_TX_DESC_CMD_L4T_EOFT_UDP		= 0x0300, /* 2 BITS */

	I40E_TX_DESC_CMD_L4T_EOFT_EOF_N		= 0x0000, /* 2 BITS */

	I40E_TX_DESC_CMD_L4T_EOFT_EOF_T		= 0x0100, /* 2 BITS */

	I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI	= 0x0200, /* 2 BITS */

	I40E_TX_DESC_CMD_L4T_EOFT_EOF_A		= 0x0300, /* 2 BITS */

	IAVF_TX_DESC_CMD_EOP			= 0x0001,

	IAVF_TX_DESC_CMD_RS			= 0x0002,

	IAVF_TX_DESC_CMD_ICRC			= 0x0004,

	IAVF_TX_DESC_CMD_IL2TAG1		= 0x0008,

	IAVF_TX_DESC_CMD_DUMMY			= 0x0010,

	IAVF_TX_DESC_CMD_IIPT_NONIP		= 0x0000, /* 2 BITS */

	IAVF_TX_DESC_CMD_IIPT_IPV6		= 0x0020, /* 2 BITS */

	IAVF_TX_DESC_CMD_IIPT_IPV4		= 0x0040, /* 2 BITS */

	IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM		= 0x0060, /* 2 BITS */

	IAVF_TX_DESC_CMD_FCOET			= 0x0080,

	IAVF_TX_DESC_CMD_L4T_EOFT_UNK		= 0x0000, /* 2 BITS */

	IAVF_TX_DESC_CMD_L4T_EOFT_TCP		= 0x0100, /* 2 BITS */

	IAVF_TX_DESC_CMD_L4T_EOFT_SCTP		= 0x0200, /* 2 BITS */

	IAVF_TX_DESC_CMD_L4T_EOFT_UDP		= 0x0300, /* 2 BITS */

	IAVF_TX_DESC_CMD_L4T_EOFT_EOF_N		= 0x0000, /* 2 BITS */

	IAVF_TX_DESC_CMD_L4T_EOFT_EOF_T		= 0x0100, /* 2 BITS */

	IAVF_TX_DESC_CMD_L4T_EOFT_EOF_NI	= 0x0200, /* 2 BITS */

	IAVF_TX_DESC_CMD_L4T_EOFT_EOF_A		= 0x0300, /* 2 BITS */

};



#define I40E_TXD_QW1_OFFSET_SHIFT	16
@@ -561,9 +561,9 @@ enum i40e_tx_desc_cmd_bits { 


enum i40e_tx_desc_length_fields {

	/* Note: These are predefined bit offsets */

	I40E_TX_DESC_LENGTH_MACLEN_SHIFT	= 0, /* 7 BITS */

	I40E_TX_DESC_LENGTH_IPLEN_SHIFT		= 7, /* 7 BITS */

	I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT	= 14 /* 4 BITS */

	IAVF_TX_DESC_LENGTH_MACLEN_SHIFT	= 0, /* 7 BITS */

	IAVF_TX_DESC_LENGTH_IPLEN_SHIFT		= 7, /* 7 BITS */

	IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT	= 14 /* 4 BITS */

};



#define I40E_TXD_QW1_TX_BUF_SZ_SHIFT	34

CRA Git | Maintained and supported by SUSTech CRA and CCSE