Commit f1ad1133 authored by Atish Patra's avatar Atish Patra Committed by Marc Zyngier
Browse files

irqchip/sifive-plic: Add support for multiple PLICs 



Current, PLIC driver can support only 1 PLIC on the board. However,
there can be multiple PLICs present on a two socket systems in RISC-V.

Modify the driver so that each PLIC handler can have a information
about individual PLIC registers and an irqdomain associated with it.

Tested on two socket RISC-V system based on VCU118 FPGA connected via
OmniXtend protocol.

Signed-off-by: default avatarAtish Patra <atish.patra@wdc.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Reviewed-by: default avatarAnup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20200302231146.15530-3-atish.patra@wdc.com
parent ccbe80ba

drivers/irqchip/irq-sifive-plic.c

+51 −30
Original line number Diff line number Diff line
@@ -59,7 +59,11 @@ 
#define	PLIC_DISABLE_THRESHOLD		0xf

#define	PLIC_ENABLE_THRESHOLD		0



static void __iomem *plic_regs;

struct plic_priv {

	struct cpumask lmask;

	struct irq_domain *irqdomain;

	void __iomem *regs;

};



struct plic_handler {

	bool			present;
@@ -70,6 +74,7 @@ struct plic_handler { 
	 */

	raw_spinlock_t		enable_lock;

	void __iomem		*enable_base;

	struct plic_priv	*priv;

};

static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
@@ -88,31 +93,40 @@ static inline void plic_toggle(struct plic_handler *handler, 
}



static inline void plic_irq_toggle(const struct cpumask *mask,

				   int hwirq, int enable)

				   struct irq_data *d, int enable)

{

	int cpu;

	struct plic_priv *priv = irq_get_chip_data(d->irq);



	writel(enable, plic_regs + PRIORITY_BASE + hwirq * PRIORITY_PER_ID);

	writel(enable, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);

	for_each_cpu(cpu, mask) {

		struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);



		if (handler->present)

			plic_toggle(handler, hwirq, enable);

		if (handler->present &&

		    cpumask_test_cpu(cpu, &handler->priv->lmask))

			plic_toggle(handler, d->hwirq, enable);

	}

}



static void plic_irq_unmask(struct irq_data *d)

{

	unsigned int cpu = cpumask_any_and(irq_data_get_affinity_mask(d),

					   cpu_online_mask);

	struct cpumask amask;

	unsigned int cpu;

	struct plic_priv *priv = irq_get_chip_data(d->irq);



	cpumask_and(&amask, &priv->lmask, cpu_online_mask);

	cpu = cpumask_any_and(irq_data_get_affinity_mask(d),

					   &amask);

	if (WARN_ON_ONCE(cpu >= nr_cpu_ids))

		return;

	plic_irq_toggle(cpumask_of(cpu), d->hwirq, 1);

	plic_irq_toggle(cpumask_of(cpu), d, 1);

}



static void plic_irq_mask(struct irq_data *d)

{

	plic_irq_toggle(cpu_possible_mask, d->hwirq, 0);

	struct plic_priv *priv = irq_get_chip_data(d->irq);



	plic_irq_toggle(&priv->lmask, d, 0);

}



#ifdef CONFIG_SMP
@@ -120,17 +134,21 @@ static int plic_set_affinity(struct irq_data *d, 
			     const struct cpumask *mask_val, bool force)

{

	unsigned int cpu;

	struct cpumask amask;

	struct plic_priv *priv = irq_get_chip_data(d->irq);



	cpumask_and(&amask, &priv->lmask, mask_val);



	if (force)

		cpu = cpumask_first(mask_val);

		cpu = cpumask_first(&amask);

	else

		cpu = cpumask_any_and(mask_val, cpu_online_mask);

		cpu = cpumask_any_and(&amask, cpu_online_mask);



	if (cpu >= nr_cpu_ids)

		return -EINVAL;



	plic_irq_toggle(cpu_possible_mask, d->hwirq, 0);

	plic_irq_toggle(cpumask_of(cpu), d->hwirq, 1);

	plic_irq_toggle(&priv->lmask, d, 0);

	plic_irq_toggle(cpumask_of(cpu), d, 1);



	irq_data_update_effective_affinity(d, cpumask_of(cpu));
@@ -191,8 +209,6 @@ static const struct irq_domain_ops plic_irqdomain_ops = { 
	.free		= irq_domain_free_irqs_top,

};



static struct irq_domain *plic_irqdomain;



/*

 * Handling an interrupt is a two-step process: first you claim the interrupt

 * by reading the claim register, then you complete the interrupt by writing
@@ -209,7 +225,7 @@ static void plic_handle_irq(struct pt_regs *regs) 


	csr_clear(CSR_IE, IE_EIE);

	while ((hwirq = readl(claim))) {

		int irq = irq_find_mapping(plic_irqdomain, hwirq);

		int irq = irq_find_mapping(handler->priv->irqdomain, hwirq);



		if (unlikely(irq <= 0))

			pr_warn_ratelimited("can't find mapping for hwirq %lu\n",
@@ -265,15 +281,17 @@ static int __init plic_init(struct device_node *node, 
{

	int error = 0, nr_contexts, nr_handlers = 0, i;

	u32 nr_irqs;

	struct plic_priv *priv;



	if (plic_regs) {

		pr_warn("PLIC already present.\n");

		return -ENXIO;

	}

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);

	if (!priv)

		return -ENOMEM;



	plic_regs = of_iomap(node, 0);

	if (WARN_ON(!plic_regs))

		return -EIO;

	priv->regs = of_iomap(node, 0);

	if (WARN_ON(!priv->regs)) {

		error = -EIO;

		goto out_free_priv;

	}



	error = -EINVAL;

	of_property_read_u32(node, "riscv,ndev", &nr_irqs);
@@ -287,9 +305,9 @@ static int __init plic_init(struct device_node *node, 
		goto out_iounmap;



	error = -ENOMEM;

	plic_irqdomain = irq_domain_add_linear(node, nr_irqs + 1,

			&plic_irqdomain_ops, NULL);

	if (WARN_ON(!plic_irqdomain))

	priv->irqdomain = irq_domain_add_linear(node, nr_irqs + 1,

			&plic_irqdomain_ops, priv);

	if (WARN_ON(!priv->irqdomain))

		goto out_iounmap;



	for (i = 0; i < nr_contexts; i++) {
@@ -334,13 +352,14 @@ static int __init plic_init(struct device_node *node, 
			goto done;

		}



		cpumask_set_cpu(cpu, &priv->lmask);

		handler->present = true;

		handler->hart_base =

			plic_regs + CONTEXT_BASE + i * CONTEXT_PER_HART;

			priv->regs + CONTEXT_BASE + i * CONTEXT_PER_HART;

		raw_spin_lock_init(&handler->enable_lock);

		handler->enable_base =

			plic_regs + ENABLE_BASE + i * ENABLE_PER_HART;



			priv->regs + ENABLE_BASE + i * ENABLE_PER_HART;

		handler->priv = priv;

done:

		for (hwirq = 1; hwirq <= nr_irqs; hwirq++)

			plic_toggle(handler, hwirq, 0);
@@ -356,7 +375,9 @@ done: 
	return 0;



out_iounmap:

	iounmap(plic_regs);

	iounmap(priv->regs);

out_free_priv:

	kfree(priv);

	return error;

}

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