Commit f1a3c0b9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'devicetree-for-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 

Pull devicetree updates from Rob Herring:
 - added Frank Rowand as DT maintainer in preparation for Grant's
   retirement.
 - generic MSI binding documentation and a few other minor doc updates
 - fix long standing issue with DT platorm device unregistration
 - fix loop forever bug in of_find_matching_node_by_address()

* tag 'devicetree-for-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
  MAINTAINERS: Add Frank Rowand as DT maintainer
  mtd: nand: pxa3xx: add optional dma for pxa architecture
  Documentation: DT: cpsw: document missing compatible
  Docs: dt: add generic MSI bindings
  drivercore: Fix unregistration path of platform devices
  of/address: Don't loop forever in of_find_matching_node_by_address().
  of: Add vendor prefix for JEDEC Solid State Technology Association
  of/platform: add function to populate default bus
  of: Add vendor prefix for Sharp Corporation
parents 089b6695 c8fb70a3

Documentation/devicetree/bindings/interrupt-controller/msi.txt

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This document describes the generic device tree binding for MSI controllers and

their master(s).



Message Signaled Interrupts (MSIs) are a class of interrupts generated by a

write to an MMIO address.



MSIs were originally specified by PCI (and are used with PCIe), but may also be

used with other busses, and hence a mechanism is required to relate devices on

those busses to the MSI controllers which they are capable of using,

potentially including additional information.



MSIs are distinguished by some combination of:



- The doorbell (the MMIO address written to).

  

  Devices may be configured by software to write to arbitrary doorbells which

  they can address. An MSI controller may feature a number of doorbells.



- The payload (the value written to the doorbell).

  

  Devices may be configured to write an arbitrary payload chosen by software.

  MSI controllers may have restrictions on permitted payloads.



- Sideband information accompanying the write.

  

  Typically this is neither configurable nor probeable, and depends on the path

  taken through the memory system (i.e. it is a property of the combination of

  MSI controller and device rather than a property of either in isolation).





MSI controllers:

================



An MSI controller signals interrupts to a CPU when a write is made to an MMIO

address by some master. An MSI controller may feature a number of doorbells.



Required properties:

--------------------



- msi-controller: Identifies the node as an MSI controller.



Optional properties:

--------------------



- #msi-cells: The number of cells in an msi-specifier, required if not zero.



  Typically this will encode information related to sideband data, and will

  not encode doorbells or payloads as these can be configured dynamically.



  The meaning of the msi-specifier is defined by the device tree binding of

  the specific MSI controller. 





MSI clients

===========



MSI clients are devices which generate MSIs. For each MSI they wish to

generate, the doorbell and payload may be configured, though sideband

information may not be configurable.



Required properties:

--------------------



- msi-parent: A list of phandle + msi-specifier pairs, one for each MSI

  controller which the device is capable of using.



  This property is unordered, and MSIs may be allocated from any combination of

  MSI controllers listed in the msi-parent property.



  If a device has restrictions on the allocation of MSIs, these restrictions

  must be described with additional properties.



  When #msi-cells is non-zero, busses with an msi-parent will require

  additional properties to describe the relationship between devices on the bus

  and the set of MSIs they can potentially generate.





Example

=======



/ {

	#address-cells = <1>;

	#size-cells = <1>;



	msi_a: msi-controller@a {

		reg = <0xa 0xf00>;

		compatible = "vendor-a,some-controller";

		msi-controller;

		/* No sideband data, so #msi-cells omitted */

	};



	msi_b: msi-controller@b {

		reg = <0xb 0xf00>;

		compatible = "vendor-b,another-controller";

		msi-controller;

		/* Each device has some unique ID */

		#msi-cells = <1>;

	};



	msi_c: msi-controller@c {

		reg = <0xb 0xf00>;

		compatible = "vendor-b,another-controller";

		msi-controller;

		/* Each device has some unique ID */

		#msi-cells = <1>;

	};



	dev@0 {

		reg = <0x0 0xf00>;

		compatible = "vendor-c,some-device";



		/* Can only generate MSIs to msi_a */

		msi-parent = <&msi_a>;

	};



	dev@1 {

		reg = <0x1 0xf00>;

		compatible = "vendor-c,some-device";



		/* 

		 * Can generate MSIs to either A or B.

		 */

		msi-parent = <&msi_a>, <&msi_b 0x17>;

	};



	dev@2 {

		reg = <0x2 0xf00>;

		compatible = "vendor-c,some-device";

		/*

		 * Has different IDs at each MSI controller.

		 * Can generate MSIs to all of the MSI controllers.

		 */

		msi-parent = <&msi_a>, <&msi_b 0x17>, <&msi_c 0x53>;

	};

};

Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt

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@@ -11,6 +11,7 @@ Required properties: 


Optional properties:



 - dmas:			dma data channel, see dma.txt binding doc

 - marvell,nand-enable-arbiter:	Set to enable the bus arbiter

 - marvell,nand-keep-config:	Set to keep the NAND controller config as set

				by the bootloader
@@ -32,6 +33,8 @@ Example: 
		compatible = "marvell,pxa3xx-nand";

		reg = <0x43100000 90>;

		interrupts = <45>;

		dmas = <&pdma 97 0>;

		dma-names = "data";

		#address-cells = <1>;



		marvell,nand-enable-arbiter;

Documentation/devicetree/bindings/net/cpsw.txt

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@@ -2,7 +2,11 @@ TI SoC Ethernet Switch Controller Device Tree Bindings 
------------------------------------------------------



Required properties:

- compatible		: Should be "ti,cpsw"

- compatible		: Should be one of the below:-

			  "ti,cpsw" for backward compatible

			  "ti,am335x-cpsw" for AM335x controllers

			  "ti,am4372-cpsw" for AM437x controllers

			  "ti,dra7-cpsw" for DRA7x controllers

- reg			: physical base address and size of the cpsw

			  registers map

- interrupts		: property with a value describing the interrupt

Documentation/devicetree/bindings/vendor-prefixes.txt

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@@ -113,6 +113,7 @@ intel Intel Corporation 
intercontrol	Inter Control Group

isee	ISEE 2007 S.L.

isil	Intersil

jedec	JEDEC Solid State Technology Association

karo	Ka-Ro electronics GmbH

keymile	Keymile GmbH

kinetic Kinetic Technologies
@@ -184,6 +185,7 @@ sbs Smart Battery System 
schindler	Schindler

seagate	Seagate Technology PLC

semtech	Semtech Corporation

sharp	Sharp Corporation

sil	Silicon Image

silabs	Silicon Laboratories

siliconmitus	Silicon Mitus, Inc.

MAINTAINERS

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@@ -7573,8 +7573,9 @@ F: Documentation/i2c/busses/i2c-ocores 
F:	drivers/i2c/busses/i2c-ocores.c



OPEN FIRMWARE AND FLATTENED DEVICE TREE

M:	Grant Likely <grant.likely@linaro.org>

M:	Rob Herring <robh+dt@kernel.org>

M:	Frank Rowand <frowand.list@gmail.com>

M:	Grant Likely <grant.likely@linaro.org>

L:	devicetree@vger.kernel.org

W:	http://www.devicetree.org/

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/glikely/linux.git

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