Commit f1a04d82 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-4.4' of git://people.freedesktop.org/~agd5f/linux into drm-next

More amdgpu and radeon stuff for drm-next.  Stoney support is the big change.
The rest is just bug fixes and code cleanups.  The Stoney stuff is pretty
low impact with respect to existing chips.

* 'drm-next-4.4' of git://people.freedesktop.org/~agd5f/linux:
  drm/amdgpu: change VM size default to 64GB
  drm/amdgpu: add Stoney pci ids
  drm/amdgpu: update the core VI support for Stoney
  drm/amdgpu: add VCE support for Stoney (v2)
  drm/amdgpu: add UVD support for Stoney
  drm/amdgpu: add GFX support for Stoney (v2)
  drm/amdgpu: add SDMA support for Stoney (v2)
  drm/amdgpu: add DCE support for Stoney
  drm/amdgpu: Update SMC/DPM for Stoney
  drm/amdgpu: add GMC support for Stoney
  drm/amdgpu: add Stoney chip family
  drm/amdgpu: fix the broken vm->mutex V2
  drm/amdgpu: remove the unnecessary parameter adev for amdgpu_fence_wait_any()
  drm/amdgpu: remove the exclusive lock
  drm/amdgpu: remove old lockup detection infrastructure
  drm: fix trivial typos
  drm/amdgpu/dce: simplify suspend/resume
  drm/amdgpu/gfx8: set TC_WB_ACTION_EN in RELEASE_MEM packet
  drm/radeon: Use rdev->gem.mutex to protect hyperz/cmask owners
parents 974e59ba ed885b21
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+1 −10
Original line number Diff line number Diff line
@@ -345,7 +345,6 @@ struct amdgpu_ring_funcs {
	/* testing functions */
	int (*test_ring)(struct amdgpu_ring *ring);
	int (*test_ib)(struct amdgpu_ring *ring);
	bool (*is_lockup)(struct amdgpu_ring *ring);
	/* insert NOP packets */
	void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
};
@@ -448,8 +447,7 @@ int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);

signed long amdgpu_fence_wait_any(struct amdgpu_device *adev,
				  struct fence **array,
signed long amdgpu_fence_wait_any(struct fence **array,
				  uint32_t count,
				  bool intr,
				  signed long t);
@@ -907,8 +905,6 @@ struct amdgpu_ring {
	unsigned		ring_size;
	unsigned		ring_free_dw;
	int			count_dw;
	atomic_t		last_rptr;
	atomic64_t		last_activity;
	uint64_t		gpu_addr;
	uint32_t		align_mask;
	uint32_t		ptr_mask;
@@ -1230,8 +1226,6 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring);
void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
void amdgpu_ring_undo(struct amdgpu_ring *ring);
void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
void amdgpu_ring_lockup_update(struct amdgpu_ring *ring);
bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring);
unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
			    uint32_t **data);
int amdgpu_ring_restore(struct amdgpu_ring *ring,
@@ -1960,7 +1954,6 @@ struct amdgpu_device {
	struct device			*dev;
	struct drm_device		*ddev;
	struct pci_dev			*pdev;
	struct rw_semaphore		exclusive_lock;

	/* ASIC */
	enum amd_asic_type		asic_type;
@@ -1974,7 +1967,6 @@ struct amdgpu_device {
	bool				suspend;
	bool				need_dma32;
	bool				accel_working;
	bool				needs_reset;
	struct work_struct 		reset_work;
	struct notifier_block		acpi_nb;
	struct amdgpu_i2c_chan		*i2c_bus[AMDGPU_MAX_I2C_BUS];
@@ -2253,7 +2245,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
#define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r))
#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
+7 −11
Original line number Diff line number Diff line
@@ -609,7 +609,6 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
		}
	}

	mutex_lock(&vm->mutex);
	r = amdgpu_bo_vm_update_pte(parser, vm);
	if (r) {
		goto out;
@@ -620,7 +619,6 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
				       parser->filp);

out:
	mutex_unlock(&vm->mutex);
	return r;
}

@@ -828,15 +826,14 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
{
	struct amdgpu_device *adev = dev->dev_private;
	union drm_amdgpu_cs *cs = data;
	struct amdgpu_fpriv *fpriv = filp->driver_priv;
	struct amdgpu_vm *vm = &fpriv->vm;
	struct amdgpu_cs_parser *parser;
	bool reserved_buffers = false;
	int i, r;

	down_read(&adev->exclusive_lock);
	if (!adev->accel_working) {
		up_read(&adev->exclusive_lock);
	if (!adev->accel_working)
		return -EBUSY;
	}

	parser = amdgpu_cs_parser_create(adev, filp, NULL, NULL, 0);
	if (!parser)
@@ -844,12 +841,11 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
	r = amdgpu_cs_parser_init(parser, data);
	if (r) {
		DRM_ERROR("Failed to initialize parser !\n");
		kfree(parser);
		up_read(&adev->exclusive_lock);
		amdgpu_cs_parser_fini(parser, r, false);
		r = amdgpu_cs_handle_lockup(adev, r);
		return r;
	}

	mutex_lock(&vm->mutex);
	r = amdgpu_cs_parser_relocs(parser);
	if (r == -ENOMEM)
		DRM_ERROR("Not enough memory for command submission!\n");
@@ -916,14 +912,14 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)

		mutex_unlock(&job->job_lock);
		amdgpu_cs_parser_fini_late(parser);
		up_read(&adev->exclusive_lock);
		mutex_unlock(&vm->mutex);
		return 0;
	}

	cs->out.handle = parser->ibs[parser->num_ibs - 1].sequence;
out:
	amdgpu_cs_parser_fini(parser, r, reserved_buffers);
	up_read(&adev->exclusive_lock);
	mutex_unlock(&vm->mutex);
	r = amdgpu_cs_handle_lockup(adev, r);
	return r;
}
+3 −11
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ static const char *amdgpu_asic_name[] = {
	"TONGA",
	"FIJI",
	"CARRIZO",
	"STONEY",
	"LAST",
};

@@ -1165,7 +1166,8 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
	case CHIP_TONGA:
	case CHIP_FIJI:
	case CHIP_CARRIZO:
		if (adev->asic_type == CHIP_CARRIZO)
	case CHIP_STONEY:
		if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
			adev->family = AMDGPU_FAMILY_CZ;
		else
			adev->family = AMDGPU_FAMILY_VI;
@@ -1418,7 +1420,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
	mutex_init(&adev->gfx.gpu_clock_mutex);
	mutex_init(&adev->srbm_mutex);
	mutex_init(&adev->grbm_idx_mutex);
	init_rwsem(&adev->exclusive_lock);
	mutex_init(&adev->mn_lock);
	hash_init(adev->mn_hash);

@@ -1814,14 +1815,6 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
	int i, r;
	int resched;

	down_write(&adev->exclusive_lock);

	if (!adev->needs_reset) {
		up_write(&adev->exclusive_lock);
		return 0;
	}

	adev->needs_reset = false;
	atomic_inc(&adev->gpu_reset_counter);

	/* block TTM */
@@ -1885,7 +1878,6 @@ retry:
		dev_info(adev->dev, "GPU reset failed\n");
	}

	up_write(&adev->exclusive_lock);
	return r;
}

+1 −6
Original line number Diff line number Diff line
@@ -47,11 +47,8 @@ static void amdgpu_flip_wait_fence(struct amdgpu_device *adev,
	fence = to_amdgpu_fence(*f);
	if (fence) {
		r = fence_wait(&fence->base, false);
		if (r == -EDEADLK) {
			up_read(&adev->exclusive_lock);
		if (r == -EDEADLK)
			r = amdgpu_gpu_reset(adev);
			down_read(&adev->exclusive_lock);
		}
	} else
		r = fence_wait(*f, false);

@@ -77,7 +74,6 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
	unsigned long flags;
	unsigned i;

	down_read(&adev->exclusive_lock);
	amdgpu_flip_wait_fence(adev, &work->excl);
	for (i = 0; i < work->shared_count; ++i)
		amdgpu_flip_wait_fence(adev, &work->shared[i]);
@@ -93,7 +89,6 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
	amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;

	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
	up_read(&adev->exclusive_lock);
}

/*
+4 −2
Original line number Diff line number Diff line
@@ -73,7 +73,7 @@ int amdgpu_hard_reset = 0;
unsigned amdgpu_ip_block_mask = 0xffffffff;
int amdgpu_bapm = -1;
int amdgpu_deep_color = 0;
int amdgpu_vm_size = 8;
int amdgpu_vm_size = 64;
int amdgpu_vm_block_size = -1;
int amdgpu_vm_fault_stop = 0;
int amdgpu_vm_debug = 0;
@@ -137,7 +137,7 @@ module_param_named(bapm, amdgpu_bapm, int, 0444);
MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
module_param_named(deep_color, amdgpu_deep_color, int, 0444);

MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 8GB)");
MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
module_param_named(vm_size, amdgpu_vm_size, int, 0444);

MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
@@ -273,6 +273,8 @@ static struct pci_device_id pciidlist[] = {
	{0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
	{0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
	{0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
	/* stoney */
	{0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},

	{0, 0, 0}
};
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