Merge tag 'clk-meson-5.2-1-fixes' of https://github.com/BayLibre/clk-meson into clk-fixes (f18d4304) · Commits · 戴 / test

drivers/clk/meson/g12a.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -2734,8 +2734,8 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
		[CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
		[CLKID_MALI_1] = &g12a_mali_1.hw,
		[CLKID_MALI] = &g12a_mali.hw,
		[CLKID_MPLL_5OM_DIV] = &g12a_mpll_50m_div.hw,
		[CLKID_MPLL_5OM] = &g12a_mpll_50m.hw,
		[CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
		[CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
		[CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
		[CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
		[CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,

+1 −1

+5 −5

Original line number	Diff line number	Diff line
		@@ -1761,7 +1761,7 @@ static struct clk_regmap meson8m2_gp_pll = {
		},
		};

		static const char * const mmeson8b_vpu_0_1_parent_names[] = {
		static const char * const meson8b_vpu_0_1_parent_names[] = {
		"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
		};

		@@ -1778,8 +1778,8 @@ static struct clk_regmap meson8b_vpu_0_sel = {
		.hw.init = &(struct clk_init_data){
		.name = "vpu_0_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = mmeson8b_vpu_0_1_parent_names,
		.num_parents = ARRAY_SIZE(mmeson8b_vpu_0_1_parent_names),
		.parent_names = meson8b_vpu_0_1_parent_names,
		.num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_names),
		.flags = CLK_SET_RATE_PARENT,
		},
		};
		@@ -1837,8 +1837,8 @@ static struct clk_regmap meson8b_vpu_1_sel = {
		.hw.init = &(struct clk_init_data){
		.name = "vpu_1_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_names = mmeson8b_vpu_0_1_parent_names,
		.num_parents = ARRAY_SIZE(mmeson8b_vpu_0_1_parent_names),
		.parent_names = meson8b_vpu_0_1_parent_names,
		.num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_names),
		.flags = CLK_SET_RATE_PARENT,
		},
		};

+1 −1