Commit f18bdfa1 authored by James Hogan's avatar James Hogan Committed by Ralf Baechle
Browse files

MIPS: Add defs & probing of [X]ContextConfig 



The CP0_[X]ContextConfig registers are present if CP0_Config3.CTXTC or
CP0_Config3.SM are set, and provide more control over which bits of
CP0_[X]Context are set to the faulting virtual address on a TLB
exception.

KVM/VZ will need to be able to save and restore these registers in the
guest context, so add the relevant definitions and probing of the
ContextConfig feature in the root context first.

[ralf@linux-mips.org: resolve merge conflict.]

Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13225/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent e06a1548

arch/mips/include/asm/cpu-features.h

+4 −0
Original line number Diff line number Diff line
@@ -450,4 +450,8 @@ 
# define cpu_has_badinstrp	(cpu_data[0].options & MIPS_CPU_BADINSTRP)

#endif



#ifndef cpu_has_contextconfig

# define cpu_has_contextconfig	(cpu_data[0].options & MIPS_CPU_CTXTC)

#endif



#endif /* __ASM_CPU_FEATURES_H */

arch/mips/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -407,6 +407,7 @@ enum cpu_type_enum { 
#define MIPS_CPU_EBASE_WG	MBIT_ULL(43)	/* CPU has EBase.WG */

#define MIPS_CPU_BADINSTR	MBIT_ULL(44)	/* CPU has BadInstr register */

#define MIPS_CPU_BADINSTRP	MBIT_ULL(45)	/* CPU has BadInstrP register */

#define MIPS_CPU_CTXTC		MBIT_ULL(46)	/* CPU has [X]ConfigContext registers */



/*

 * CPU ASE encodings

arch/mips/include/asm/mipsregs.h

+6 −0
Original line number Diff line number Diff line
@@ -1228,9 +1228,15 @@ do { \ 
#define read_c0_context()	__read_ulong_c0_register($4, 0)

#define write_c0_context(val)	__write_ulong_c0_register($4, 0, val)



#define read_c0_contextconfig()		__read_32bit_c0_register($4, 1)

#define write_c0_contextconfig(val)	__write_32bit_c0_register($4, 1, val)



#define read_c0_userlocal()	__read_ulong_c0_register($4, 2)

#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)



#define read_c0_xcontextconfig()	__read_ulong_c0_register($4, 3)

#define write_c0_xcontextconfig(val)	__write_ulong_c0_register($4, 3, val)



#define read_c0_pagemask()	__read_32bit_c0_register($5, 0)

#define write_c0_pagemask(val)	__write_32bit_c0_register($5, 0, val)

arch/mips/kernel/cpu-probe.c

+3 −1
Original line number Diff line number Diff line
@@ -687,10 +687,12 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) 


	if (config3 & MIPS_CONF3_SM) {

		c->ases |= MIPS_ASE_SMARTMIPS;

		c->options |= MIPS_CPU_RIXI;

		c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;

	}

	if (config3 & MIPS_CONF3_RXI)

		c->options |= MIPS_CPU_RIXI;

	if (config3 & MIPS_CONF3_CTXTC)

		c->options |= MIPS_CPU_CTXTC;

	if (config3 & MIPS_CONF3_DSP)

		c->ases |= MIPS_ASE_DSP;

	if (config3 & MIPS_CONF3_DSP2P) {

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