Commit f1857a24 authored by Kan Liang's avatar Kan Liang Committed by Ingo Molnar
Browse files

perf/x86/cstate: Update C-state counters for Ice Lake 



There is no Core C3 C-State counter for Ice Lake.
Package C8/C9/C10 C-State counters are added for Ice Lake.

Introduce a new event list, icl_cstates, for Ice Lake.
Update the comments accordingly.

Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Fixes: f08c47d1 ("perf/x86/intel/cstate: Add Icelake support")
Link: https://lkml.kernel.org/r/1570549810-25049-7-git-send-email-kan.liang@linux.intel.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 1a5da78d

arch/x86/events/intel/cstate.c

+25 −11
Original line number Diff line number Diff line
@@ -50,43 +50,44 @@ 
 *	MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter

 *			       perf code: 0x02

 *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,

 *						SKL,KNL,GLM,CNL,KBL,CML

 *						SKL,KNL,GLM,CNL,KBL,CML,ICL

 *			       Scope: Core

 *	MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter

 *			       perf code: 0x03

 *			       Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML

 *			       Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,

 *						ICL

 *			       Scope: Core

 *	MSR_PKG_C2_RESIDENCY:  Package C2 Residency Counter.

 *			       perf code: 0x00

 *			       Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,

 *						KBL,CML

 *						KBL,CML,ICL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C3_RESIDENCY:  Package C3 Residency Counter.

 *			       perf code: 0x01

 *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,

 *						GLM,CNL,KBL,CML

 *						GLM,CNL,KBL,CML,ICL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C6_RESIDENCY:  Package C6 Residency Counter.

 *			       perf code: 0x02

 *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW

 *						SKL,KNL,GLM,CNL,KBL,CML

 *						SKL,KNL,GLM,CNL,KBL,CML,ICL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C7_RESIDENCY:  Package C7 Residency Counter.

 *			       perf code: 0x03

 *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL,

 *						KBL,CML

 *						KBL,CML,ICL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C8_RESIDENCY:  Package C8 Residency Counter.

 *			       perf code: 0x04

 *			       Available model: HSW ULT,KBL,CNL,CML

 *			       Available model: HSW ULT,KBL,CNL,CML,ICL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C9_RESIDENCY:  Package C9 Residency Counter.

 *			       perf code: 0x05

 *			       Available model: HSW ULT,KBL,CNL,CML

 *			       Available model: HSW ULT,KBL,CNL,CML,ICL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.

 *			       perf code: 0x06

 *			       Available model: HSW ULT,KBL,GLM,CNL,CML

 *			       Available model: HSW ULT,KBL,GLM,CNL,CML,ICL

 *			       Scope: Package (physical package)

 *

 */
@@ -546,6 +547,19 @@ static const struct cstate_model cnl_cstates __initconst = { 
				  BIT(PERF_CSTATE_PKG_C10_RES),

};



static const struct cstate_model icl_cstates __initconst = {

	.core_events		= BIT(PERF_CSTATE_CORE_C6_RES) |

				  BIT(PERF_CSTATE_CORE_C7_RES),



	.pkg_events		= BIT(PERF_CSTATE_PKG_C2_RES) |

				  BIT(PERF_CSTATE_PKG_C3_RES) |

				  BIT(PERF_CSTATE_PKG_C6_RES) |

				  BIT(PERF_CSTATE_PKG_C7_RES) |

				  BIT(PERF_CSTATE_PKG_C8_RES) |

				  BIT(PERF_CSTATE_PKG_C9_RES) |

				  BIT(PERF_CSTATE_PKG_C10_RES),

};



static const struct cstate_model slm_cstates __initconst = {

	.core_events		= BIT(PERF_CSTATE_CORE_C1_RES) |

				  BIT(PERF_CSTATE_CORE_C6_RES),
@@ -629,8 +643,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { 


	X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_PLUS, glm_cstates),



	X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, snb_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE,   snb_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, icl_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE,   icl_cstates),

	{ },

};

MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);

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