arm64: entry: Reword comment about post_ttbr_update_workaround (f167211a) · Commits · 戴 / test

We don't fully understand the Cavium ThunderX erratum, but it appears that mapping the kernel as nG can lead to horrible consequences such as attempting to execute userspace from kernel context. Since kpti isn't enabled for these CPUs anyway, simplify the comment justifying the lack of post_ttbr_update_workaround in the exception trampoline. Signed-off-by:

Will Deacon <will.deacon@arm.com> Signed-off-by:

Catalin Marinas <catalin.marinas@arm.com>

arch/arm64/kernel/entry.S

+3 −10

Original line number	Diff line number	Diff line
		@@ -1013,16 +1013,9 @@ alternative_else_nop_endif
		orr \tmp, \tmp, #USER_ASID_FLAG
		msr ttbr1_el1, \tmp
		/*
		* We avoid running the post_ttbr_update_workaround here because the
		* user and kernel ASIDs don't have conflicting mappings, so any
		* "blessing" as described in:
		*
		* http://lkml.kernel.org/r/56BB848A.6060603@caviumnetworks.com
		*
		* will not hurt correctness. Whilst this may partially defeat the
		* point of using split ASIDs in the first place, it avoids
		* the hit of invalidating the entire I-cache on every return to
		* userspace.
		* We avoid running the post_ttbr_update_workaround here because
		* it's only needed by Cavium ThunderX, which requires KPTI to be
		* disabled.
		*/
		.endm

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