Commit f150abe1 authored by Russell King's avatar Russell King
Browse files

Merge branch 'for-next' of git://git.pengutronix.de/git/ukl/linux into devel-stable 

Pull ARM-v7M support from Uwe Kleine-König:
"All but the last patch were in next since next-20130418 without issues.
The last patch fixes a problem in combination with

  8164f7af (ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 register)

which triggers a WARN_ON without an implemented read_cpuid_ext.

The branch merges fine into v3.10-rc1 and I'd be happy if you pulled it
for 3.11-rc1. The only missing piece to be able to run a Cortex-M3 is
the irqchip driver that will go in via Thomas Gleixner and platform
specific stuff."
parents 519fe2ec 6fae9cda

arch/arm/Kconfig

+2 −2
Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ config ARM 
	select BUILDTIME_EXTABLE_SORT if MMU

	select CPU_PM if (SUSPEND || CPU_IDLE)

	select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU

	select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)

	select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)

	select GENERIC_CLOCKEVENTS_BROADCAST if SMP

	select GENERIC_IRQ_PROBE

	select GENERIC_IRQ_SHOW
@@ -1585,7 +1585,7 @@ config SCHED_HRTICK 


config THUMB2_KERNEL

	bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY

	depends on CPU_V7 && !CPU_V6 && !CPU_V6K

	depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K

	default y if CPU_THUMBONLY

	select AEABI

	select ARM_ASM_UNIFIED

arch/arm/Kconfig-nommu

+1 −1
Original line number Diff line number Diff line
@@ -28,7 +28,7 @@ config FLASH_SIZE 
config PROCESSOR_ID

	hex 'Hard wire the processor ID'

	default 0x00007700

	depends on !CPU_CP15

	depends on !(CPU_CP15 || CPU_V7M)

	help

	  If processor has no CP15 register, this processor ID is

	  used instead of the auto-probing which utilizes the register.

arch/arm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@ comma = , 
# Note that GCC does not numerically define an architecture version

# macro, but instead defines a whole series of macros which makes

# testing for a specific architecture or later rather impossible.

arch-$(CONFIG_CPU_32v7M)	:=-D__LINUX_ARM_ARCH__=7 -march=armv7-m -Wa,-march=armv7-m

arch-$(CONFIG_CPU_32v7)		:=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)

arch-$(CONFIG_CPU_32v6)		:=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)

# Only override the compiler option if ARMv6. The ARMv6K extensions are

arch/arm/include/asm/assembler.h

+16 −1
Original line number Diff line number Diff line
@@ -136,7 +136,11 @@ 
 * assumes FIQs are enabled, and that the processor is in SVC mode.

 */

	.macro	save_and_disable_irqs, oldcpsr

#ifdef CONFIG_CPU_V7M

	mrs	\oldcpsr, primask

#else

	mrs	\oldcpsr, cpsr

#endif

	disable_irq

	.endm
@@ -150,7 +154,11 @@ 
 * guarantee that this will preserve the flags.

 */

	.macro	restore_irqs_notrace, oldcpsr

#ifdef CONFIG_CPU_V7M

	msr	primask, \oldcpsr

#else

	msr	cpsr_c, \oldcpsr

#endif

	.endm



	.macro restore_irqs, oldcpsr
@@ -229,7 +237,14 @@ 
#endif

	.endm



#ifdef CONFIG_THUMB2_KERNEL

#if defined(CONFIG_CPU_V7M)

	/*

	 * setmode is used to assert to be in svc mode during boot. For v7-M

	 * this is done in __v7m_setup, so setmode can be empty here.

	 */

	.macro	setmode, mode, reg

	.endm

#elif defined(CONFIG_THUMB2_KERNEL)

	.macro	setmode, mode, reg

	mov	\reg, #\mode

	msr	cpsr_c, \reg

arch/arm/include/asm/cputype.h

+42 −2
Original line number Diff line number Diff line
@@ -10,6 +10,22 @@ 
#define CPUID_TLBTYPE	3

#define CPUID_MPIDR	5



#ifdef CONFIG_CPU_V7M

#define CPUID_EXT_PFR0	0x40

#define CPUID_EXT_PFR1	0x44

#define CPUID_EXT_DFR0	0x48

#define CPUID_EXT_AFR0	0x4c

#define CPUID_EXT_MMFR0	0x50

#define CPUID_EXT_MMFR1	0x54

#define CPUID_EXT_MMFR2	0x58

#define CPUID_EXT_MMFR3	0x5c

#define CPUID_EXT_ISAR0	0x60

#define CPUID_EXT_ISAR1	0x64

#define CPUID_EXT_ISAR2	0x68

#define CPUID_EXT_ISAR3	0x6c

#define CPUID_EXT_ISAR4	0x70

#define CPUID_EXT_ISAR5	0x74

#else

#define CPUID_EXT_PFR0	"c1, 0"

#define CPUID_EXT_PFR1	"c1, 1"

#define CPUID_EXT_DFR0	"c1, 2"
@@ -24,6 +40,7 @@ 
#define CPUID_EXT_ISAR3	"c2, 3"

#define CPUID_EXT_ISAR4	"c2, 4"

#define CPUID_EXT_ISAR5	"c2, 5"

#endif



#define MPIDR_SMP_BITMASK (0x3 << 30)

#define MPIDR_SMP_VALUE (0x2 << 30)
@@ -79,7 +96,23 @@ extern unsigned int processor_id; 
		__val;							\

	})



#else /* ifdef CONFIG_CPU_CP15 */

#elif defined(CONFIG_CPU_V7M)



#include <asm/io.h>

#include <asm/v7m.h>



#define read_cpuid(reg)							\

	({								\

		WARN_ON_ONCE(1);					\

		0;							\

	})



static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)

{

	return readl(BASEADDR_V7M_SCB + offset);

}



#else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */



/*

 * read_cpuid and read_cpuid_ext should only ever be called on machines that
@@ -106,7 +139,14 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void) 
	return read_cpuid(CPUID_ID);

}



#else /* ifdef CONFIG_CPU_CP15 */

#elif defined(CONFIG_CPU_V7M)



static inline unsigned int __attribute_const__ read_cpuid_id(void)

{

	return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);

}



#else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */



static inline unsigned int __attribute_const__ read_cpuid_id(void)

{

CRA Git | Maintained and supported by SUSTech CRA and CCSE