Commit f12da687 authored by zain wang's avatar zain wang Committed by Andrzej Hajda
Browse files

drm/bridge: analogix_dp: Fix AUX_PD bit for Rockchip 



There are some different bits between Rockchip and Exynos in register
"AUX_PD". This patch fixes the incorrect operations about it.

Cc: Douglas Anderson <dianders@chromium.org>
Signed-off-by: default avatarzain wang <wzz@rock-chips.com>
Signed-off-by: default avatarSean Paul <seanpaul@chromium.org>
Signed-off-by: default avatarThierry Escande <thierry.escande@collabora.com>
Reviewed-by: default avatarAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: default avatarEnric Balletbo i Serra <enric.balletbo@collabora.com>
Tested-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: default avatarArchit Taneja <architt@codeaurora.org>
Signed-off-by: default avatarAndrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180423105003.9004-12-enric.balletbo@collabora.com
parent ccdc578b

drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c

+63 −54
Original line number Diff line number Diff line
@@ -248,76 +248,85 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 
{

	u32 reg;

	u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;

	u32 mask;



	if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))

		phy_pd_addr = ANALOGIX_DP_PD;



	switch (block) {

	case AUX_BLOCK:

		if (enable) {

			reg = readl(dp->reg_base + phy_pd_addr);

			reg |= AUX_PD;

			writel(reg, dp->reg_base + phy_pd_addr);

		} else {

		if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))

			mask = RK_AUX_PD;

		else

			mask = AUX_PD;



		reg = readl(dp->reg_base + phy_pd_addr);

			reg &= ~AUX_PD;

		if (enable)

			reg |= mask;

		else

			reg &= ~mask;

		writel(reg, dp->reg_base + phy_pd_addr);

		}

		break;

	case CH0_BLOCK:

		if (enable) {

		mask = CH0_PD;

		reg = readl(dp->reg_base + phy_pd_addr);

			reg |= CH0_PD;

			writel(reg, dp->reg_base + phy_pd_addr);

		} else {

			reg = readl(dp->reg_base + phy_pd_addr);

			reg &= ~CH0_PD;



		if (enable)

			reg |= mask;

		else

			reg &= ~mask;

		writel(reg, dp->reg_base + phy_pd_addr);

		}

		break;

	case CH1_BLOCK:

		if (enable) {

			reg = readl(dp->reg_base + phy_pd_addr);

			reg |= CH1_PD;

			writel(reg, dp->reg_base + phy_pd_addr);

		} else {

		mask = CH1_PD;

		reg = readl(dp->reg_base + phy_pd_addr);

			reg &= ~CH1_PD;



		if (enable)

			reg |= mask;

		else

			reg &= ~mask;

		writel(reg, dp->reg_base + phy_pd_addr);

		}

		break;

	case CH2_BLOCK:

		if (enable) {

		mask = CH2_PD;

		reg = readl(dp->reg_base + phy_pd_addr);

			reg |= CH2_PD;

			writel(reg, dp->reg_base + phy_pd_addr);

		} else {

			reg = readl(dp->reg_base + phy_pd_addr);

			reg &= ~CH2_PD;



		if (enable)

			reg |= mask;

		else

			reg &= ~mask;

		writel(reg, dp->reg_base + phy_pd_addr);

		}

		break;

	case CH3_BLOCK:

		if (enable) {

			reg = readl(dp->reg_base + phy_pd_addr);

			reg |= CH3_PD;

			writel(reg, dp->reg_base + phy_pd_addr);

		} else {

		mask = CH3_PD;

		reg = readl(dp->reg_base + phy_pd_addr);

			reg &= ~CH3_PD;



		if (enable)

			reg |= mask;

		else

			reg &= ~mask;

		writel(reg, dp->reg_base + phy_pd_addr);

		}

		break;

	case ANALOG_TOTAL:

		if (enable) {

			reg = readl(dp->reg_base + phy_pd_addr);

			reg |= DP_PHY_PD;

			writel(reg, dp->reg_base + phy_pd_addr);

		} else {

		/*

		 * There is no bit named DP_PHY_PD, so We used DP_INC_BG

		 * to power off everything instead of DP_PHY_PD in

		 * Rockchip

		 */

		if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))

			mask = DP_INC_BG;

		else

			mask = DP_PHY_PD;



		reg = readl(dp->reg_base + phy_pd_addr);

			reg &= ~DP_PHY_PD;

		if (enable)

			reg |= mask;

		else

			reg &= ~mask;



		writel(reg, dp->reg_base + phy_pd_addr);

		}

		if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))

			usleep_range(10, 15);

		break;

	case POWER_ALL:

		if (enable) {

drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -345,7 +345,9 @@ 
#define DP_INC_BG				(0x1 << 7)

#define DP_EXP_BG				(0x1 << 6)

#define DP_PHY_PD				(0x1 << 5)

#define RK_AUX_PD				(0x1 << 5)

#define AUX_PD					(0x1 << 4)

#define RK_PLL_PD				(0x1 << 4)

#define CH3_PD					(0x1 << 3)

#define CH2_PD					(0x1 << 2)

#define CH1_PD					(0x1 << 1)

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