drm/i915: Per-pipe PP registers are for VLV only

#define  LVDS_DETECTED	(1 << 1)

/* vlv has 2 sets of panel control regs. */

#define PIPEA_PP_STATUS         0x61200

#define PIPEA_PP_CONTROL        0x61204

#define PIPEA_PP_ON_DELAYS      0x61208

#define PIPEA_PP_OFF_DELAYS     0x6120c

#define PIPEA_PP_DIVISOR        0x61210

#define PIPEB_PP_STATUS         0x61300

#define PIPEB_PP_CONTROL        0x61304

#define PIPEB_PP_ON_DELAYS      0x61308

#define PIPEB_PP_OFF_DELAYS     0x6130c

#define PIPEB_PP_DIVISOR        0x61310

#define PIPEA_PP_STATUS         (VLV_DISPLAY_BASE + 0x61200)

#define PIPEA_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61204)

#define PIPEA_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61208)

#define PIPEA_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6120c)

#define PIPEA_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61210)

#define PIPEB_PP_STATUS         (VLV_DISPLAY_BASE + 0x61300)

#define PIPEB_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61304)

#define PIPEB_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61308)

#define PIPEB_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6130c)

#define PIPEB_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61310)

#define PCH_PP_STATUS		0xc7200

#define PCH_PP_CONTROL		0xc7204