r8169: avoid losing MSI interrupts (f11a377b) · Commits · 戴 / test

drivers/net/r8169.c

+57 −45

Original line number	Diff line number	Diff line
		@@ -3554,43 +3554,43 @@ static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
		int handled = 0;
		int status;

		/* loop handling interrupts until we have no new ones or
		* we hit a invalid/hotplug case.
		*/
		status = RTL_R16(IntrStatus);

		/* hotplug/major error/no more work/shared irq */
		if ((status == 0xffff) \|\| !status)
		goto out;

		while (status && status != 0xffff) {
		handled = 1;

		/* Handle all of the error cases first. These will reset
		* the chip, so just exit the loop.
		*/
		if (unlikely(!netif_running(dev))) {
		rtl8169_asic_down(ioaddr);
		goto out;
		break;
		}

		status &= tp->intr_mask;
		RTL_W16(IntrStatus,
		(status & RxFIFOOver) ? (status \| RxOverflow) : status);

		if (!(status & tp->intr_event))
		goto out;

		/* Work around for rx fifo overflow */
		if (unlikely(status & RxFIFOOver) &&
		(tp->mac_version == RTL_GIGA_MAC_VER_11)) {
		netif_stop_queue(dev);
		rtl8169_tx_timeout(dev);
		goto out;
		break;
		}

		if (unlikely(status & SYSErr)) {
		rtl8169_pcierr_interrupt(dev);
		goto out;
		break;
		}

		if (status & LinkChg)
		rtl8169_check_link_status(dev, tp, ioaddr);

		if (status & tp->napi_event) {
		/* We need to see the lastest version of tp->intr_mask to
		* avoid ignoring an MSI interrupt and having to wait for
		* another event which may never come.
		*/
		smp_rmb();
		if (status & tp->intr_mask & tp->napi_event) {
		RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
		tp->intr_mask = ~tp->napi_event;

		@@ -3601,7 +3601,17 @@ static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
		dev->name, status);
		}
		}
		out:

		/* We only get a new MSI interrupt when all active irq
		* sources on the chip have been acknowledged. So, ack
		* everything we've seen and check if new sources have become
		* active to avoid blocking all interrupts from the chip.
		*/
		RTL_W16(IntrStatus,
		(status & RxFIFOOver) ? (status \| RxOverflow) : status);
		status = RTL_R16(IntrStatus);
		}

		return IRQ_RETVAL(handled);
		}

		@@ -3617,13 +3627,15 @@ static int rtl8169_poll(struct napi_struct *napi, int budget)

		if (work_done < budget) {
		napi_complete(napi);
		tp->intr_mask = 0xffff;
		/*
		* 20040426: the barrier is not strictly required but the
		* behavior of the irq handler could be less predictable
		* without it. Btw, the lack of flush for the posted pci
		* write is safe - FR

		/* We need for force the visibility of tp->intr_mask
		* for other CPUs, as we can loose an MSI interrupt
		* and potentially wait for a retransmit timeout if we don't.
		* The posted write to IntrMask is safe, as it will
		* eventually make it to the chip and we won't loose anything
		* until it does.
		*/
		tp->intr_mask = 0xffff;
		smp_wmb();
		RTL_W16(IntrMask, tp->intr_event);
		}

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