Commit f0c4b8d6 authored by Will Deacon's avatar Will Deacon Committed by Russell King
Browse files

ARM: 7396/1: errata: only handle ARM erratum #326103 on affected cores 

Erratum #326103 ("FSR write bit incorrect on a SWP to read-only memory")
only affects the ARM 1136 core prior to r1p0. The workaround
disassembles the faulting instruction to determine whether it was a read
or write access on all v6 cores.

An issue has been reported on the ARM 11MPCore whereby loading the
faulting instruction may happen in parallel with that page being
unmapped, resulting in a deadlock due to the lack of TLB broadcasting
in hardware:

http://lists.infradead.org/pipermail/linux-arm-kernel/2012-March/091561.html



This patch limits the workaround so that it is only used on affected
cores, which are known to be UP only. Other v6 cores can rely on the
FSR to indicate the access type correctly.

Cc: stable@vger.kernel.org
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent e895bd79

arch/arm/Kconfig

+9 −0
Original line number Original line Diff line number Diff line
@@ -1186,6 +1186,15 @@ if !MMU 
source "arch/arm/Kconfig-nommu"

source "arch/arm/Kconfig-nommu"

endif

endif





config ARM_ERRATA_326103

	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"

	depends on CPU_V6

	help

	  Executing a SWP instruction to read-only memory does not set bit 11

	  of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to

	  treat the access as a read, preventing a COW from occurring and

	  causing the faulting task to livelock.



config ARM_ERRATA_411920

config ARM_ERRATA_411920

	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"

	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"

	depends on CPU_V6 || CPU_V6K

	depends on CPU_V6 || CPU_V6K

arch/arm/mm/abort-ev6.S

+11 −6
Original line number Original line Diff line number Diff line
@@ -26,18 +26,23 @@ ENTRY(v6_early_abort) 
	mrc	p15, 0, r1, c5, c0, 0		@ get FSR

	mrc	p15, 0, r1, c5, c0, 0		@ get FSR

	mrc	p15, 0, r0, c6, c0, 0		@ get FAR

	mrc	p15, 0, r0, c6, c0, 0		@ get FAR

/*

/*

 * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103).

 * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR.

 * The test below covers all the write situations, including Java bytecodes

 */

 */

	bic	r1, r1, #1 << 11		@ clear bit 11 of FSR

#ifdef CONFIG_ARM_ERRATA_326103

	ldr	ip, =0x4107b36

	mrc	p15, 0, r3, c0, c0, 0		@ get processor id

	teq	ip, r3, lsr #4			@ r0 ARM1136?

	bne	do_DataAbort

	tst	r5, #PSR_J_BIT			@ Java?

	tst	r5, #PSR_J_BIT			@ Java?

	tsteq	r5, #PSR_T_BIT			@ Thumb?

	bne	do_DataAbort

	bne	do_DataAbort

	do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3

	bic	r1, r1, #1 << 11		@ clear bit 11 of FSR

	ldreq	r3, [r4]			@ read aborted ARM instruction

	ldr	r3, [r4]			@ read aborted ARM instruction

#ifdef CONFIG_CPU_ENDIAN_BE8

#ifdef CONFIG_CPU_ENDIAN_BE8

	reveq	r3, r3

	rev	r3, r3

#endif

#endif

	do_ldrd_abort tmp=ip, insn=r3

	do_ldrd_abort tmp=ip, insn=r3

	tst	r3, #1 << 20			@ L = 0 -> write

	tst	r3, #1 << 20			@ L = 0 -> write

	orreq	r1, r1, #1 << 11		@ yes.

	orreq	r1, r1, #1 << 11		@ yes.

#endif

	b	do_DataAbort
 
	b	do_DataAbort

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