Commit f0c2aa16 authored by Fabrizio Castro's avatar Fabrizio Castro Committed by Simon Horman
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arm64: dts: renesas: r8a774c0: Add PCIe device node



This patch adds PCI express channel 0 device tree node to the
RZ/G2E (a.k.a. R8A774C0) SoC dtsi.

Signed-off-by: default avatarFabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 52a20e64
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+27 −0
Original line number Diff line number Diff line
@@ -1418,6 +1418,33 @@
			resets = <&cpg 408>;
		};

		pciec0: pcie@fe000000 {
			compatible = "renesas,pcie-r8a774c0",
				     "renesas,pcie-rcar-gen3";
			reg = <0 0xfe000000 0 0x80000>;
			#address-cells = <3>;
			#size-cells = <2>;
			bus-range = <0x00 0xff>;
			device_type = "pci";
			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
				  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
				  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
				  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
			/* Map all possible DDR as inbound ranges */
			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
			clock-names = "pcie", "pcie_bus";
			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
			resets = <&cpg 319>;
			status = "disabled";
		};

		vspb0: vsp@fe960000 {
			compatible = "renesas,vsp2";
			reg = <0 0xfe960000 0 0x8000>;