Commit f09991ad authored by Wu Hao's avatar Wu Hao Committed by Moritz Fischer
Browse files

fpga: dfl: afu: add userclock sysfs interfaces. 



This patch introduces userclock sysfs interfaces for AFU, user
could use these interfaces for clock setting to AFU.

Please note that, this is only working for port header feature
with revision 0, for later revisions, userclock setting is moved
to a separated private feature, so one revision sysfs interface
is exposed to userspace application for this purpose too.

Signed-off-by: default avatarAnanda Ravuri <ananda.ravuri@intel.com>
Signed-off-by: default avatarRuss Weight <russell.h.weight@intel.com>
Signed-off-by: default avatarXu Yilun <yilun.xu@intel.com>
Signed-off-by: default avatarWu Hao <hao.wu@intel.com>
Acked-by: default avatarAlan Tull <atull@kernel.org>
Signed-off-by: default avatarMoritz Fischer <mdf@kernel.org>
parent a80a4b82

Documentation/ABI/testing/sysfs-platform-dfl-port

+28 −0
Original line number Diff line number Diff line
@@ -46,3 +46,31 @@ Contact: Wu Hao <hao.wu@intel.com> 
Description:	Read-write. Read or set AFU latency tolerance reporting value.

		Set ltr to 1 if the AFU can tolerate latency >= 40us or set it

		to 0 if it is latency sensitive.



What:		/sys/bus/platform/devices/dfl-port.0/userclk_freqcmd

Date:		August 2019

KernelVersion:	5.4

Contact:	Wu Hao <hao.wu@intel.com>

Description:	Write-only. User writes command to this interface to set

		userclock to AFU.



What:		/sys/bus/platform/devices/dfl-port.0/userclk_freqsts

Date:		August 2019

KernelVersion:	5.4

Contact:	Wu Hao <hao.wu@intel.com>

Description:	Read-only. Read this file to get the status of issued command

		to userclck_freqcmd.



What:		/sys/bus/platform/devices/dfl-port.0/userclk_freqcntrcmd

Date:		August 2019

KernelVersion:	5.4

Contact:	Wu Hao <hao.wu@intel.com>

Description:	Write-only. User writes command to this interface to set

		userclock counter.



What:		/sys/bus/platform/devices/dfl-port.0/userclk_freqcntrsts

Date:		August 2019

KernelVersion:	5.4

Contact:	Wu Hao <hao.wu@intel.com>

Description:	Read-only. Read this file to get the status of issued command

		to userclck_freqcntrcmd.

drivers/fpga/dfl-afu-main.c

+110 −1
Original line number Diff line number Diff line
@@ -274,17 +274,126 @@ power_state_show(struct device *dev, struct device_attribute *attr, char *buf) 
}

static DEVICE_ATTR_RO(power_state);



static ssize_t

userclk_freqcmd_store(struct device *dev, struct device_attribute *attr,

		      const char *buf, size_t count)

{

	struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);

	u64 userclk_freq_cmd;

	void __iomem *base;



	if (kstrtou64(buf, 0, &userclk_freq_cmd))

		return -EINVAL;



	base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);



	mutex_lock(&pdata->lock);

	writeq(userclk_freq_cmd, base + PORT_HDR_USRCLK_CMD0);

	mutex_unlock(&pdata->lock);



	return count;

}

static DEVICE_ATTR_WO(userclk_freqcmd);



static ssize_t

userclk_freqcntrcmd_store(struct device *dev, struct device_attribute *attr,

			  const char *buf, size_t count)

{

	struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);

	u64 userclk_freqcntr_cmd;

	void __iomem *base;



	if (kstrtou64(buf, 0, &userclk_freqcntr_cmd))

		return -EINVAL;



	base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);



	mutex_lock(&pdata->lock);

	writeq(userclk_freqcntr_cmd, base + PORT_HDR_USRCLK_CMD1);

	mutex_unlock(&pdata->lock);



	return count;

}

static DEVICE_ATTR_WO(userclk_freqcntrcmd);



static ssize_t

userclk_freqsts_show(struct device *dev, struct device_attribute *attr,

		     char *buf)

{

	struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);

	u64 userclk_freqsts;

	void __iomem *base;



	base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);



	mutex_lock(&pdata->lock);

	userclk_freqsts = readq(base + PORT_HDR_USRCLK_STS0);

	mutex_unlock(&pdata->lock);



	return sprintf(buf, "0x%llx\n", (unsigned long long)userclk_freqsts);

}

static DEVICE_ATTR_RO(userclk_freqsts);



static ssize_t

userclk_freqcntrsts_show(struct device *dev, struct device_attribute *attr,

			 char *buf)

{

	struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);

	u64 userclk_freqcntrsts;

	void __iomem *base;



	base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);



	mutex_lock(&pdata->lock);

	userclk_freqcntrsts = readq(base + PORT_HDR_USRCLK_STS1);

	mutex_unlock(&pdata->lock);



	return sprintf(buf, "0x%llx\n",

		       (unsigned long long)userclk_freqcntrsts);

}

static DEVICE_ATTR_RO(userclk_freqcntrsts);



static struct attribute *port_hdr_attrs[] = {

	&dev_attr_id.attr,

	&dev_attr_ltr.attr,

	&dev_attr_ap1_event.attr,

	&dev_attr_ap2_event.attr,

	&dev_attr_power_state.attr,

	&dev_attr_userclk_freqcmd.attr,

	&dev_attr_userclk_freqcntrcmd.attr,

	&dev_attr_userclk_freqsts.attr,

	&dev_attr_userclk_freqcntrsts.attr,

	NULL,

};



static umode_t port_hdr_attrs_visible(struct kobject *kobj,

				      struct attribute *attr, int n)

{

	struct device *dev = kobj_to_dev(kobj);

	umode_t mode = attr->mode;

	void __iomem *base;



	base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);



	if (dfl_feature_revision(base) > 0) {

		/*

		 * userclk sysfs interfaces are only visible in case port

		 * revision is 0, as hardware with revision >0 doesn't

		 * support this.

		 */

		if (attr == &dev_attr_userclk_freqcmd.attr ||

		    attr == &dev_attr_userclk_freqcntrcmd.attr ||

		    attr == &dev_attr_userclk_freqsts.attr ||

		    attr == &dev_attr_userclk_freqcntrsts.attr)

			mode = 0;

	}



	return mode;

}



static const struct attribute_group port_hdr_group = {

	.attrs      = port_hdr_attrs,

	.is_visible = port_hdr_attrs_visible,

};



static int port_hdr_init(struct platform_device *pdev,

drivers/fpga/dfl.h

+9 −0
Original line number Diff line number Diff line
@@ -120,6 +120,10 @@ 
#define PORT_HDR_CAP		0x30

#define PORT_HDR_CTRL		0x38

#define PORT_HDR_STS		0x40

#define PORT_HDR_USRCLK_CMD0	0x50

#define PORT_HDR_USRCLK_CMD1	0x58

#define PORT_HDR_USRCLK_STS0	0x60

#define PORT_HDR_USRCLK_STS1	0x68



/* Port Capability Register Bitfield */

#define PORT_CAP_PORT_NUM	GENMASK_ULL(1, 0)	/* ID of this port */
@@ -355,6 +359,11 @@ static inline bool dfl_feature_is_port(void __iomem *base) 
		(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT);

}



static inline u8 dfl_feature_revision(void __iomem *base)

{

	return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH));

}



/**

 * struct dfl_fpga_enum_info - DFL FPGA enumeration information

 *

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