Commit f07b56e7 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'for-airlie-armada' of git://git.armlinux.org.uk/~rmk/linux-arm into drm-next 



Armada DRM updates:
- Fix interlace support.
- use __drm_atomic_helper_plane_reset in overlay reset.
- since the overlay and video planes use essentially the same format
  registers, precompute their values while validating.
- fix a long-standing deficiency with overlay planes and interlace modes
- calculate plane starting address at atomic_check stage rather than
  when we're programming the registers.
- add gamma support.
- ensure mode adjustments made by other components are properly handled
  in the driver and applied to the CRTC-programmed mode.
- add and use register definitions for the "REG4F" register.
- use drm_atomic_helper_shutdown() when tearing down to ensure that the
  hardware is properly shutdown.
- add CRTC-level mode validation to ensure that we don't allow a mode
  that the CRTC-level hardware can not support.
- improve the clocking selection for Armada 510 support.
- move CRTC debugfs files into the crtc-specific directory, using the
  DRM helper to create these files.
- patch from Lubomir Rintel to replace a simple framebuffer.
- use the OF graph walker rather than open-coding this.
- eliminate a useless check for the availability of the remote's parent
  which isn't required.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Russell King <rmk@armlinux.org.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190702091313.GA23442@rmk-PC.armlinux.org.uk
parents a22719cc 837567c1

drivers/gpu/drm/armada/armada_510.c

+93 −37
Original line number Diff line number Diff line
@@ -14,18 +14,62 @@ 
#include "armada_drm.h"

#include "armada_hw.h"



struct armada510_variant_data {

	struct clk *clks[4];

	struct clk *sel_clk;

};



static int armada510_crtc_init(struct armada_crtc *dcrtc, struct device *dev)

{

	struct armada510_variant_data *v;

	struct clk *clk;



	int idx;



	v = devm_kzalloc(dev, sizeof(*v), GFP_KERNEL);

	if (!v)

		return -ENOMEM;



	dcrtc->variant_data = v;



	if (dev->of_node) {

		struct property *prop;

		const char *s;



		of_property_for_each_string(dev->of_node, "clock-names", prop,

					    s) {

			if (!strcmp(s, "ext_ref_clk0"))

				idx = 0;

			else if (!strcmp(s, "ext_ref_clk1"))

				idx = 1;

			else if (!strcmp(s, "plldivider"))

				idx = 2;

			else if (!strcmp(s, "axibus"))

				idx = 3;

			else

				continue;



			clk = devm_clk_get(dev, s);

			if (IS_ERR(clk))

				return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER :

					PTR_ERR(clk);

			v->clks[idx] = clk;

		}

	} else {

		clk = devm_clk_get(dev, "ext_ref_clk1");

		if (IS_ERR(clk))

		return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER : PTR_ERR(clk);

			return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER :

				PTR_ERR(clk);



	dcrtc->extclk[0] = clk;

		v->clks[1] = clk;

	}



	/* Lower the watermark so to eliminate jitter at higher bandwidths */

	armada_updatel(0x20, (1 << 11) | 0xff, dcrtc->base + LCD_CFG_RDREG4F);

	/*

	 * Lower the watermark so to eliminate jitter at higher bandwidths.

	 * Disable SRAM read wait state to avoid system hang with external

	 * clock.

	 */

	armada_updatel(CFG_DMA_WM(0x20), CFG_SRAM_WAIT | CFG_DMA_WM_MASK,

		       dcrtc->base + LCD_CFG_RDREG4F);



	/* Initialise SPU register */

	writel_relaxed(ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND,
@@ -34,65 +78,77 @@ static int armada510_crtc_init(struct armada_crtc *dcrtc, struct device *dev) 
	return 0;

}



static const u32 armada510_clk_sels[] = {

	SCLK_510_EXTCLK0,

	SCLK_510_EXTCLK1,

	SCLK_510_PLL,

	SCLK_510_AXI,

};



static const struct armada_clocking_params armada510_clocking = {

	/* HDMI requires -0.6%..+0.5% */

	.permillage_min = 994,

	.permillage_max = 1005,

	.settable = BIT(0) | BIT(1),

	.div_max = SCLK_510_INT_DIV_MASK,

};



/*

 * Armada510 specific SCLK register selection.

 * This gets called with sclk = NULL to test whether the mode is

 * supportable, and again with sclk != NULL to set the clocks up for

 * that.  The former can return an error, but the latter is expected

 * not to.

 *

 * We currently are pretty rudimentary here, always selecting

 * EXT_REF_CLK_1 for LCD0 and erroring LCD1.  This needs improvement!

 */

static int armada510_crtc_compute_clock(struct armada_crtc *dcrtc,

	const struct drm_display_mode *mode, uint32_t *sclk)

{

	struct clk *clk = dcrtc->extclk[0];

	int ret;



	if (dcrtc->num == 1)

		return -EINVAL;



	if (IS_ERR(clk))

		return PTR_ERR(clk);



	if (dcrtc->clk != clk) {

		ret = clk_prepare_enable(clk);

	struct armada510_variant_data *v = dcrtc->variant_data;

	unsigned long desired_khz = mode->crtc_clock;

	struct armada_clk_result res;

	int ret, idx;



	idx = armada_crtc_select_clock(dcrtc, &res, &armada510_clocking,

				       v->clks, ARRAY_SIZE(v->clks),

				       desired_khz);

	if (idx < 0)

		return idx;



	ret = clk_prepare_enable(res.clk);

	if (ret)

		return ret;

		dcrtc->clk = clk;

	}



	if (sclk) {

		uint32_t rate, ref, div;

		clk_set_rate(res.clk, res.desired_clk_hz);



		rate = mode->clock * 1000;

		ref = clk_round_rate(clk, rate);

		div = DIV_ROUND_UP(ref, rate);

		if (div < 1)

			div = 1;

		*sclk = res.div | armada510_clk_sels[idx];



		clk_set_rate(clk, ref);

		*sclk = div | SCLK_510_EXTCLK1;

		/* We are now using this clock */

		v->sel_clk = res.clk;

		swap(dcrtc->clk, res.clk);

	}



	clk_disable_unprepare(res.clk);



	return 0;

}



static void armada510_crtc_disable(struct armada_crtc *dcrtc)

{

	if (!IS_ERR(dcrtc->clk)) {

	if (dcrtc->clk) {

		clk_disable_unprepare(dcrtc->clk);

		dcrtc->clk = ERR_PTR(-EINVAL);

		dcrtc->clk = NULL;

	}

}



static void armada510_crtc_enable(struct armada_crtc *dcrtc,

	const struct drm_display_mode *mode)

{

	if (IS_ERR(dcrtc->clk)) {

		dcrtc->clk = dcrtc->extclk[0];

		WARN_ON(clk_prepare_enable(dcrtc->clk));

	struct armada510_variant_data *v = dcrtc->variant_data;



	if (!dcrtc->clk && v->sel_clk) {

		if (!WARN_ON(clk_prepare_enable(v->sel_clk)))

			dcrtc->clk = v->sel_clk;

	}

}

drivers/gpu/drm/armada/armada_crtc.c

+202 −12
Original line number Diff line number Diff line
@@ -130,6 +130,70 @@ static void armada_drm_crtc_queue_state_event(struct drm_crtc *crtc) 
	}

}



static void armada_drm_update_gamma(struct drm_crtc *crtc)

{

	struct drm_property_blob *blob = crtc->state->gamma_lut;

	void __iomem *base = drm_to_armada_crtc(crtc)->base;

	int i;



	if (blob) {

		struct drm_color_lut *lut = blob->data;



		armada_updatel(CFG_CSB_256x8, CFG_CSB_256x8 | CFG_PDWN256x8,

			       base + LCD_SPU_SRAM_PARA1);



		for (i = 0; i < 256; i++) {

			writel_relaxed(drm_color_lut_extract(lut[i].red, 8),

				       base + LCD_SPU_SRAM_WRDAT);

			writel_relaxed(i | SRAM_WRITE | SRAM_GAMMA_YR,

				       base + LCD_SPU_SRAM_CTRL);

			readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);

			writel_relaxed(drm_color_lut_extract(lut[i].green, 8),

				       base + LCD_SPU_SRAM_WRDAT);

			writel_relaxed(i | SRAM_WRITE | SRAM_GAMMA_UG,

				       base + LCD_SPU_SRAM_CTRL);

			readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);

			writel_relaxed(drm_color_lut_extract(lut[i].blue, 8),

				       base + LCD_SPU_SRAM_WRDAT);

			writel_relaxed(i | SRAM_WRITE | SRAM_GAMMA_VB,

				       base + LCD_SPU_SRAM_CTRL);

			readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);

		}

		armada_updatel(CFG_GAMMA_ENA, CFG_GAMMA_ENA,

			       base + LCD_SPU_DMA_CTRL0);

	} else {

		armada_updatel(0, CFG_GAMMA_ENA, base + LCD_SPU_DMA_CTRL0);

		armada_updatel(CFG_PDWN256x8, CFG_CSB_256x8 | CFG_PDWN256x8,

			       base + LCD_SPU_SRAM_PARA1);

	}

}



static enum drm_mode_status armada_drm_crtc_mode_valid(struct drm_crtc *crtc,

	const struct drm_display_mode *mode)

{

	struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);



	if (mode->vscan > 1)

		return MODE_NO_VSCAN;



	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)

		return MODE_NO_DBLESCAN;



	if (mode->flags & DRM_MODE_FLAG_HSKEW)

		return MODE_H_ILLEGAL;



	/* We can't do interlaced modes if we don't have the SPU_ADV_REG */

	if (!dcrtc->variant->has_spu_adv_reg &&

	    mode->flags & DRM_MODE_FLAG_INTERLACE)

		return MODE_NO_INTERLACE;



	if (mode->flags & (DRM_MODE_FLAG_BCAST | DRM_MODE_FLAG_PIXMUX |

			   DRM_MODE_FLAG_CLKDIV2))

		return MODE_BAD;



	return MODE_OK;

}



/* The mode_config.mutex will be held for this call */

static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,

	const struct drm_display_mode *mode, struct drm_display_mode *adj)
@@ -137,9 +201,18 @@ static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc, 
	struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);

	int ret;



	/* We can't do interlaced modes if we don't have the SPU_ADV_REG */

	if (!dcrtc->variant->has_spu_adv_reg &&

	    adj->flags & DRM_MODE_FLAG_INTERLACE)

	/*

	 * Set CRTC modesetting parameters for the adjusted mode.  This is

	 * applied after the connectors, bridges, and encoders have fixed up

	 * this mode, as described above drm_atomic_helper_check_modeset().

	 */

	drm_mode_set_crtcinfo(adj, CRTC_INTERLACE_HALVE_V);



	/*

	 * Validate the adjusted mode in case an encoder/bridge has set

	 * something we don't support.

	 */

	if (armada_drm_crtc_mode_valid(crtc, adj) != MODE_OK)

		return false;



	/* Check whether the display mode is possible */
@@ -278,16 +351,9 @@ static void armada_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 


	armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);



	if (interlaced ^ dcrtc->interlaced) {

		if (adj->flags & DRM_MODE_FLAG_INTERLACE)

			drm_crtc_vblank_get(&dcrtc->crtc);

		else

			drm_crtc_vblank_put(&dcrtc->crtc);

		dcrtc->interlaced = interlaced;

	}



	spin_lock_irqsave(&dcrtc->irq_lock, flags);



	dcrtc->interlaced = interlaced;

	/* Even interlaced/progressive frame */

	dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |

				    adj->crtc_htotal;
@@ -345,6 +411,20 @@ static void armada_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 
	spin_unlock_irqrestore(&dcrtc->irq_lock, flags);

}



static int armada_drm_crtc_atomic_check(struct drm_crtc *crtc,

					struct drm_crtc_state *state)

{

	DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);



	if (state->gamma_lut && drm_color_lut_size(state->gamma_lut) != 256)

		return -EINVAL;



	if (state->color_mgmt_changed)

		state->planes_changed = true;



	return 0;

}



static void armada_drm_crtc_atomic_begin(struct drm_crtc *crtc,

					 struct drm_crtc_state *old_crtc_state)

{
@@ -352,6 +432,9 @@ static void armada_drm_crtc_atomic_begin(struct drm_crtc *crtc, 


	DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);



	if (crtc->state->color_mgmt_changed)

		armada_drm_update_gamma(crtc);



	dcrtc->regs_idx = 0;

	dcrtc->regs = dcrtc->atomic_regs;

}
@@ -390,6 +473,9 @@ static void armada_drm_crtc_atomic_disable(struct drm_crtc *crtc, 


	DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);



	if (old_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)

		drm_crtc_vblank_put(crtc);



	drm_crtc_vblank_off(crtc);

	armada_drm_crtc_update(dcrtc, false);
@@ -434,12 +520,17 @@ static void armada_drm_crtc_atomic_enable(struct drm_crtc *crtc, 
	armada_drm_crtc_update(dcrtc, true);

	drm_crtc_vblank_on(crtc);



	if (crtc->state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)

		WARN_ON(drm_crtc_vblank_get(crtc));



	armada_drm_crtc_queue_state_event(crtc);

}



static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {

	.mode_valid	= armada_drm_crtc_mode_valid,

	.mode_fixup	= armada_drm_crtc_mode_fixup,

	.mode_set_nofb	= armada_drm_crtc_mode_set_nofb,

	.atomic_check	= armada_drm_crtc_atomic_check,

	.atomic_begin	= armada_drm_crtc_atomic_begin,

	.atomic_flush	= armada_drm_crtc_atomic_flush,

	.atomic_disable	= armada_drm_crtc_atomic_disable,
@@ -460,6 +551,13 @@ static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix, 
		for (x = 0; x < width; x++, p++) {

			uint32_t val = *p;



			/*

			 * In "ARGB888" (HWC32) mode, writing to the SRAM

			 * requires these bits to contain:

			 * 31:24 = alpha 23:16 = blue 15:8 = green 7:0 = red

			 * So, it's actually ABGR8888.  This is independent

			 * of the SWAPRB bits in DMA control register 0.

			 */

			val = (val & 0xff00ff00) |

			      (val & 0x000000ff) << 16 |

			      (val & 0x00ff0000) >> 16;
@@ -676,6 +774,14 @@ static void armada_drm_crtc_destroy(struct drm_crtc *crtc) 
	kfree(dcrtc);

}



static int armada_drm_crtc_late_register(struct drm_crtc *crtc)

{

	if (IS_ENABLED(CONFIG_DEBUG_FS))

		armada_drm_crtc_debugfs_init(drm_to_armada_crtc(crtc));



	return 0;

}



/* These are called under the vbl_lock. */

static int armada_drm_crtc_enable_vblank(struct drm_crtc *crtc)

{
@@ -703,14 +809,93 @@ static const struct drm_crtc_funcs armada_crtc_funcs = { 
	.cursor_set	= armada_drm_crtc_cursor_set,

	.cursor_move	= armada_drm_crtc_cursor_move,

	.destroy	= armada_drm_crtc_destroy,

	.gamma_set	= drm_atomic_helper_legacy_gamma_set,

	.set_config	= drm_atomic_helper_set_config,

	.page_flip	= drm_atomic_helper_page_flip,

	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,

	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,

	.late_register	= armada_drm_crtc_late_register,

	.enable_vblank	= armada_drm_crtc_enable_vblank,

	.disable_vblank	= armada_drm_crtc_disable_vblank,

};



int armada_crtc_select_clock(struct armada_crtc *dcrtc,

			     struct armada_clk_result *res,

			     const struct armada_clocking_params *params,

			     struct clk *clks[], size_t num_clks,

			     unsigned long desired_khz)

{

	unsigned long desired_hz = desired_khz * 1000;

	unsigned long desired_clk_hz;	// requested clk input

	unsigned long real_clk_hz;	// actual clk input

	unsigned long real_hz;		// actual pixel clk

	unsigned long permillage;

	struct clk *clk;

	u32 div;

	int i;



	DRM_DEBUG_KMS("[CRTC:%u:%s] desired clock=%luHz\n",

		      dcrtc->crtc.base.id, dcrtc->crtc.name, desired_hz);



	for (i = 0; i < num_clks; i++) {

		clk = clks[i];

		if (!clk)

			continue;



		if (params->settable & BIT(i)) {

			real_clk_hz = clk_round_rate(clk, desired_hz);

			desired_clk_hz = desired_hz;

		} else {

			real_clk_hz = clk_get_rate(clk);

			desired_clk_hz = real_clk_hz;

		}



		/* If the clock can do exactly the desired rate, we're done */

		if (real_clk_hz == desired_hz) {

			real_hz = real_clk_hz;

			div = 1;

			goto found;

		}



		/* Calculate the divider - if invalid, we can't do this rate */

		div = DIV_ROUND_CLOSEST(real_clk_hz, desired_hz);

		if (div == 0 || div > params->div_max)

			continue;



		/* Calculate the actual rate - HDMI requires -0.6%..+0.5% */

		real_hz = DIV_ROUND_CLOSEST(real_clk_hz, div);



		DRM_DEBUG_KMS("[CRTC:%u:%s] clk=%u %luHz div=%u real=%luHz\n",

			dcrtc->crtc.base.id, dcrtc->crtc.name,

			i, real_clk_hz, div, real_hz);



		/* Avoid repeated division */

		if (real_hz < desired_hz) {

			permillage = real_hz / desired_khz;

			if (permillage < params->permillage_min)

				continue;

		} else {

			permillage = DIV_ROUND_UP(real_hz, desired_khz);

			if (permillage > params->permillage_max)

				continue;

		}

		goto found;

	}



	return -ERANGE;



found:

	DRM_DEBUG_KMS("[CRTC:%u:%s] selected clk=%u %luHz div=%u real=%luHz\n",

		dcrtc->crtc.base.id, dcrtc->crtc.name,

		i, real_clk_hz, div, real_hz);



	res->desired_clk_hz = desired_clk_hz;

	res->clk = clk;

	res->div = div;



	return i;

}



static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,

	struct resource *res, int irq, const struct armada_variant *variant,

	struct device_node *port)
@@ -737,7 +922,6 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev, 
	dcrtc->variant = variant;

	dcrtc->base = base;

	dcrtc->num = drm->mode_config.num_crtc;

	dcrtc->clk = ERR_PTR(-EINVAL);

	dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;

	dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;

	spin_lock_init(&dcrtc->irq_lock);
@@ -794,6 +978,12 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev, 


	drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);



	ret = drm_mode_crtc_set_gamma_size(&dcrtc->crtc, 256);

	if (ret)

		return ret;



	drm_crtc_enable_color_mgmt(&dcrtc->crtc, 0, false, 256);



	return armada_overlay_plane_create(drm, 1 << dcrtc->num);



err_crtc_init:

drivers/gpu/drm/armada/armada_crtc.h

+20 −1
Original line number Diff line number Diff line
@@ -39,10 +39,10 @@ struct armada_variant; 
struct armada_crtc {

	struct drm_crtc		crtc;

	const struct armada_variant *variant;

	void			*variant_data;

	unsigned		num;

	void __iomem		*base;

	struct clk		*clk;

	struct clk		*extclk[2];

	struct {

		uint32_t	spu_v_h_total;

		uint32_t	spu_v_porch;
@@ -75,6 +75,25 @@ struct armada_crtc { 


void armada_drm_crtc_update_regs(struct armada_crtc *, struct armada_regs *);



struct armada_clocking_params {

	unsigned long permillage_min;

	unsigned long permillage_max;

	u32 settable;

	u32 div_max;

};



struct armada_clk_result {

	unsigned long desired_clk_hz;

	struct clk *clk;

	u32 div;

};



int armada_crtc_select_clock(struct armada_crtc *dcrtc,

			     struct armada_clk_result *res,

			     const struct armada_clocking_params *params,

			     struct clk *clks[], size_t num_clks,

			     unsigned long desired_khz);



extern struct platform_driver armada_lcd_platform_driver;



#endif

drivers/gpu/drm/armada/armada_debugfs.c

+38 −60
Original line number Diff line number Diff line
@@ -28,50 +28,33 @@ static int armada_debugfs_gem_linear_show(struct seq_file *m, void *data) 
	return 0;

}



static int armada_debugfs_reg_show(struct seq_file *m, void *data)

static int armada_debugfs_crtc_reg_show(struct seq_file *m, void *data)

{

	struct drm_device *dev = m->private;

	struct armada_private *priv = dev->dev_private;

	int n, i;



	if (priv) {

		for (n = 0; n < ARRAY_SIZE(priv->dcrtc); n++) {

			struct armada_crtc *dcrtc = priv->dcrtc[n];

			if (!dcrtc)

				continue;

	struct armada_crtc *dcrtc = m->private;

	int i;



	for (i = 0x84; i <= 0x1c4; i += 4) {

				uint32_t v = readl_relaxed(dcrtc->base + i);

				seq_printf(m, "%u: 0x%04x: 0x%08x\n", n, i, v);

			}

		}

		u32 v = readl_relaxed(dcrtc->base + i);

		seq_printf(m, "0x%04x: 0x%08x\n", i, v);

	}



	return 0;

}



static int armada_debugfs_reg_r_open(struct inode *inode, struct file *file)

static int armada_debugfs_crtc_reg_open(struct inode *inode, struct file *file)

{

	return single_open(file, armada_debugfs_reg_show, inode->i_private);

	return single_open(file, armada_debugfs_crtc_reg_show,

			   inode->i_private);

}



static const struct file_operations fops_reg_r = {

	.owner = THIS_MODULE,

	.open = armada_debugfs_reg_r_open,

	.read = seq_read,

	.llseek = seq_lseek,

	.release = single_release,

};



static int armada_debugfs_write(struct file *file, const char __user *ptr,

	size_t len, loff_t *off)

static int armada_debugfs_crtc_reg_write(struct file *file,

	const char __user *ptr, size_t len, loff_t *off)

{

	struct drm_device *dev = file->private_data;

	struct armada_private *priv = dev->dev_private;

	struct armada_crtc *dcrtc = priv->dcrtc[0];

	char buf[32], *p;

	uint32_t reg, val;

	struct armada_crtc *dcrtc;

	unsigned long reg, mask, val;

	char buf[32];

	int ret;

	u32 v;



	if (*off != 0)

		return 0;
@@ -84,24 +67,35 @@ static int armada_debugfs_write(struct file *file, const char __user *ptr, 
		return ret;

	buf[len] = '\0';



	reg = simple_strtoul(buf, &p, 16);

	if (!isspace(*p))

	if (sscanf(buf, "%lx %lx %lx", &reg, &mask, &val) != 3)

		return -EINVAL;

	val = simple_strtoul(p + 1, NULL, 16);

	if (reg < 0x84 || reg > 0x1c4 || reg & 3)

		return -ERANGE;



	if (reg >= 0x84 && reg <= 0x1c4)

		writel(val, dcrtc->base + reg);

	dcrtc = ((struct seq_file *)file->private_data)->private;

	v = readl(dcrtc->base + reg);

	v &= ~mask;

	v |= val & mask;

	writel(v, dcrtc->base + reg);



	return len;

}



static const struct file_operations fops_reg_w = {

static const struct file_operations armada_debugfs_crtc_reg_fops = {

	.owner = THIS_MODULE,

	.open = simple_open,

	.write = armada_debugfs_write,

	.llseek = noop_llseek,

	.open = armada_debugfs_crtc_reg_open,

	.read = seq_read,

	.write = armada_debugfs_crtc_reg_write,

	.llseek = seq_lseek,

	.release = single_release,

};



void armada_drm_crtc_debugfs_init(struct armada_crtc *dcrtc)

{

	debugfs_create_file("armada-regs", 0600, dcrtc->crtc.debugfs_entry,

			    dcrtc, &armada_debugfs_crtc_reg_fops);

}



static struct drm_info_list armada_debugfs_list[] = {

	{ "gem_linear", armada_debugfs_gem_linear_show, 0 },

};
@@ -109,24 +103,8 @@ static struct drm_info_list armada_debugfs_list[] = { 


int armada_drm_debugfs_init(struct drm_minor *minor)

{

	struct dentry *de;

	int ret;



	ret = drm_debugfs_create_files(armada_debugfs_list,

				       ARMADA_DEBUGFS_ENTRIES,

	drm_debugfs_create_files(armada_debugfs_list, ARMADA_DEBUGFS_ENTRIES,

				 minor->debugfs_root, minor);

	if (ret)

		return ret;



	de = debugfs_create_file("reg", S_IFREG | S_IRUSR,

				 minor->debugfs_root, minor->dev, &fops_reg_r);

	if (!de)

		return -ENOMEM;



	de = debugfs_create_file("reg_wr", S_IFREG | S_IWUSR,

				 minor->debugfs_root, minor->dev, &fops_reg_w);

	if (!de)

		return -ENOMEM;



	return 0;

}

drivers/gpu/drm/armada/armada_drm.h

+1 −0
Original line number Diff line number Diff line
@@ -78,6 +78,7 @@ void armada_fbdev_fini(struct drm_device *); 


int armada_overlay_plane_create(struct drm_device *, unsigned long);



void armada_drm_crtc_debugfs_init(struct armada_crtc *dcrtc);

int armada_drm_debugfs_init(struct drm_minor *);



#endif

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