Commit f03c7aa4 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'lorenzo/pci/dwc' 

  - reduce Keystone "link already up" log level (Fabio Estevam)

  - move private DT functions to drivers/pci/ (Rob Herring)

  - factor out dwc CONFIG_PCI Kconfig dependencies (Rob Herring)

  - add DesignWare support to the endpoint test driver (Gustavo Pimentel)

  - add DesignWare support for endpoint mode (Gustavo Pimentel)

  - use devm_ioremap_resource() instead of devm_ioremap() in dra7xx and
    artpec6 (Gustavo Pimentel)

  - fix Qualcomm bitwise NOT issue (Dan Carpenter)

  - add Qualcomm runtime PM support (Srinivas Kandagatla)

* lorenzo/pci/dwc:
  PCI: qcom: add runtime pm support to pcie_port
  PCI: qcom: Fix a bitwise vs logical NOT typo
  PCI: dwc: dra7xx: Use devm_ioremap_resource() instead of devm_ioremap()
  PCI: dwc: artpec6: Use devm_ioremap_resource() instead of devm_ioremap()
  misc: pci_endpoint_test: Add DesignWare EP entry
  dt-bindings: PCI: designware: Add support for EP in DesignWare driver
  PCI: dwc: Add support for EP mode
  dt-bindings: PCI: designware: Example update
  PCI: Move private DT related functions into private header
  PCI: dwc: Move CONFIG_PCI depends to menu
  PCI: dwc: Replace magic number by defines
  PCI: dwc: Small computation improvement
  PCI: dwc: Replace lower into upper case characters
  PCI: dwc: Define maximum number of vectors
  PCI: imx6: Remove space before tabs
  PCI: keystone: Do not treat link up message as error

# Conflicts:
#	include/linux/of_pci.h
parents bdc4bb13 854b69ef

Documentation/devicetree/bindings/pci/designware-pcie.txt

+18 −6
Original line number Diff line number Diff line 
* Synopsys DesignWare PCIe interface



Required properties:

- compatible: should contain "snps,dw-pcie" to identify the core.

- compatible:

	"snps,dw-pcie" for RC mode;

	"snps,dw-pcie-ep" for EP mode;

- reg: Should contain the configuration address space.

- reg-names: Must be "config" for the PCIe configuration space.

    (The old way of getting the configuration address space from "ranges"
@@ -41,11 +43,11 @@ EP mode: 


Example configuration:



	pcie: pcie@dffff000 {

	pcie: pcie@dfc00000 {

		compatible = "snps,dw-pcie";

		reg = <0xdffff000 0x1000>, /* Controller registers */

		      <0xd0000000 0x2000>; /* PCI config space */

		reg-names = "ctrlreg", "config";

		reg = <0xdfc00000 0x0001000>, /* IP registers */

		      <0xd0000000 0x0002000>; /* Configuration space */

		reg-names = "dbi", "config";

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";
@@ -54,5 +56,15 @@ Example configuration: 
		interrupts = <25>, <24>;

		#interrupt-cells = <1>;

		num-lanes = <1>;

		num-viewport = <3>;

	};

or

	pcie: pcie@dfc00000 {

		compatible = "snps,dw-pcie-ep";

		reg = <0xdfc00000 0x0001000>, /* IP registers 1 */

		      <0xdfc01000 0x0001000>, /* IP registers 2 */

		      <0xd0000000 0x2000000>; /* Configuration space */

		reg-names = "dbi", "dbi2", "addr_space";

		num-ib-windows = <6>;

		num-ob-windows = <2>;

		num-lanes = <1>;

	};

drivers/misc/pci_endpoint_test.c

+1 −0
Original line number Diff line number Diff line
@@ -634,6 +634,7 @@ static void pci_endpoint_test_remove(struct pci_dev *pdev) 
static const struct pci_device_id pci_endpoint_test_tbl[] = {

	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },

	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },

	{ PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, 0xedda) },

	{ }

};

MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);

drivers/pci/dwc/Kconfig

+32 −22
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0



menu "DesignWare PCI Core Support"

	depends on PCI



config PCIE_DW

	bool



config PCIE_DW_HOST

        bool

	depends on PCI

	depends on PCI_MSI_IRQ_DOMAIN

        select PCIE_DW
@@ -22,7 +22,7 @@ config PCI_DRA7XX 
config PCI_DRA7XX_HOST

	bool "TI DRA7xx PCIe controller Host Mode"

	depends on SOC_DRA7XX || COMPILE_TEST

	depends on PCI && PCI_MSI_IRQ_DOMAIN

	depends on PCI_MSI_IRQ_DOMAIN

	depends on OF && HAS_IOMEM && TI_PIPE3

	select PCIE_DW_HOST

	select PCI_DRA7XX
@@ -51,21 +51,40 @@ config PCI_DRA7XX_EP 
	  This uses the DesignWare core.



config PCIE_DW_PLAT

	bool "Platform bus based DesignWare PCIe Controller"

	depends on PCI

	depends on PCI_MSI_IRQ_DOMAIN

	select PCIE_DW_HOST

	---help---

	 This selects the DesignWare PCIe controller support. Select this if

	 you have a PCIe controller on Platform bus.

	bool



	 If you have a controller with this interface, say Y or M here.

config PCIE_DW_PLAT_HOST

	bool "Platform bus based DesignWare PCIe Controller - Host mode"

	depends on PCI && PCI_MSI_IRQ_DOMAIN

	select PCIE_DW_HOST

	select PCIE_DW_PLAT

	default y

	help

	  Enables support for the PCIe controller in the Designware IP to

	  work in host mode. There are two instances of PCIe controller in

	  Designware IP.

	  This controller can work either as EP or RC. In order to enable

	  host-specific features PCIE_DW_PLAT_HOST must be selected and in

	  order to enable device-specific features PCI_DW_PLAT_EP must be

	  selected.



	 If unsure, say N.

config PCIE_DW_PLAT_EP

	bool "Platform bus based DesignWare PCIe Controller - Endpoint mode"

	depends on PCI && PCI_MSI_IRQ_DOMAIN

	depends on PCI_ENDPOINT

	select PCIE_DW_EP

	select PCIE_DW_PLAT

	help

	  Enables support for the PCIe controller in the Designware IP to

	  work in endpoint mode. There are two instances of PCIe controller

	  in Designware IP.

	  This controller can work either as EP or RC. In order to enable

	  host-specific features PCIE_DW_PLAT_HOST must be selected and in

	  order to enable device-specific features PCI_DW_PLAT_EP must be

	  selected.



config PCI_EXYNOS

	bool "Samsung Exynos PCIe controller"

	depends on PCI

	depends on SOC_EXYNOS5440

	depends on PCI_MSI_IRQ_DOMAIN

	select PCIEPORTBUS
@@ -73,7 +92,6 @@ config PCI_EXYNOS 


config PCI_IMX6

	bool "Freescale i.MX6 PCIe controller"

	depends on PCI

	depends on SOC_IMX6Q

	depends on PCI_MSI_IRQ_DOMAIN

	select PCIEPORTBUS
@@ -81,7 +99,6 @@ config PCI_IMX6 


config PCIE_SPEAR13XX

	bool "STMicroelectronics SPEAr PCIe controller"

	depends on PCI

	depends on ARCH_SPEAR13XX

	depends on PCI_MSI_IRQ_DOMAIN

	select PCIEPORTBUS
@@ -91,7 +108,6 @@ config PCIE_SPEAR13XX 


config PCI_KEYSTONE

	bool "TI Keystone PCIe controller"

	depends on PCI

	depends on ARCH_KEYSTONE

	depends on PCI_MSI_IRQ_DOMAIN

	select PCIEPORTBUS
@@ -104,7 +120,6 @@ config PCI_KEYSTONE 


config PCI_LAYERSCAPE

	bool "Freescale Layerscape PCIe controller"

	depends on PCI

	depends on OF && (ARM || ARCH_LAYERSCAPE)

	depends on PCI_MSI_IRQ_DOMAIN

	select MFD_SYSCON
@@ -115,7 +130,6 @@ config PCI_LAYERSCAPE 
config PCI_HISI

	depends on OF && ARM64

	bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers"

	depends on PCI

	depends on PCI_MSI_IRQ_DOMAIN

	select PCIEPORTBUS

	select PCIE_DW_HOST
@@ -126,7 +140,6 @@ config PCI_HISI 


config PCIE_QCOM

	bool "Qualcomm PCIe controller"

	depends on PCI

	depends on ARCH_QCOM && OF

	depends on PCI_MSI_IRQ_DOMAIN

	select PCIEPORTBUS
@@ -138,7 +151,6 @@ config PCIE_QCOM 


config PCIE_ARMADA_8K

	bool "Marvell Armada-8K PCIe controller"

	depends on PCI

	depends on ARCH_MVEBU

	depends on PCI_MSI_IRQ_DOMAIN

	select PCIEPORTBUS
@@ -155,7 +167,7 @@ config PCIE_ARTPEC6 
config PCIE_ARTPEC6_HOST

	bool "Axis ARTPEC-6 PCIe controller Host Mode"

	depends on MACH_ARTPEC6

	depends on PCI && PCI_MSI_IRQ_DOMAIN

	depends on PCI_MSI_IRQ_DOMAIN

	select PCIEPORTBUS

	select PCIE_DW_HOST

	select PCIE_ARTPEC6
@@ -177,7 +189,6 @@ config PCIE_KIRIN 
	depends on OF && ARM64

	bool "HiSilicon Kirin series SoCs PCIe controllers"

	depends on PCI_MSI_IRQ_DOMAIN

	depends on PCI

	select PCIEPORTBUS

	select PCIE_DW_HOST

	help
@@ -187,7 +198,6 @@ config PCIE_KIRIN 
config PCIE_HISI_STB

	bool "HiSilicon STB SoCs PCIe controllers"

	depends on ARCH_HISI

	depends on PCI

	depends on PCI_MSI_IRQ_DOMAIN

	select PCIEPORTBUS

	select PCIE_DW_HOST

drivers/pci/dwc/pci-dra7xx.c

+10 −9
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ 
#include <linux/mfd/syscon.h>

#include <linux/regmap.h>



#include "../pci.h"

#include "pcie-designware.h"



/* PCIe controller wrapper DRA7XX configuration registers */
@@ -406,14 +407,14 @@ static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx, 
	ep->ops = &pcie_ep_ops;



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics");

	pci->dbi_base = devm_ioremap(dev, res->start, resource_size(res));

	if (!pci->dbi_base)

		return -ENOMEM;

	pci->dbi_base = devm_ioremap_resource(dev, res);

	if (IS_ERR(pci->dbi_base))

		return PTR_ERR(pci->dbi_base);



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics2");

	pci->dbi_base2 = devm_ioremap(dev, res->start, resource_size(res));

	if (!pci->dbi_base2)

		return -ENOMEM;

	pci->dbi_base2 = devm_ioremap_resource(dev, res);

	if (IS_ERR(pci->dbi_base2))

		return PTR_ERR(pci->dbi_base2);



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");

	if (!res)
@@ -459,9 +460,9 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, 
		return ret;



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");

	pci->dbi_base = devm_ioremap(dev, res->start, resource_size(res));

	if (!pci->dbi_base)

		return -ENOMEM;

	pci->dbi_base = devm_ioremap_resource(dev, res);

	if (IS_ERR(pci->dbi_base))

		return PTR_ERR(pci->dbi_base);



	pp->ops = &dra7xx_pcie_host_ops;

drivers/pci/dwc/pci-keystone.c

+1 −1
Original line number Diff line number Diff line
@@ -89,7 +89,7 @@ static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie) 
	dw_pcie_setup_rc(pp);



	if (dw_pcie_link_up(pci)) {

		dev_err(dev, "Link already up\n");

		dev_info(dev, "Link already up\n");

		return 0;

	}

CRA Git | Maintained and supported by SUSTech CRA and CCSE