Commit f02cbbe6 authored by Chris Metcalf's avatar Chris Metcalf
Browse files

pci root complex: support for tile architecture 



This change enables PCI root complex support for TILEPro.  Unlike
TILE-Gx, TILEPro has no support for memory-mapped I/O, so the PCI
support consists of hypervisor upcalls for PIO, DMA, etc.  However,
the performance is fine for the devices we have tested with so far
(1Gb Ethernet, SATA, etc.).

The <asm/io.h> header was tweaked to be a little bit more aggressive
about disabling attempts to map/unmap IO port space.  The hacky
<asm/pci-bridge.h> header was rolled into the <asm/pci.h> header
and the result was simplified.  Both of the latter two headers were
preliminary versions not meant for release before now - oh well.

There is one quirk for our TILEmpower platform, which accidentally
negotiates up to 5GT and needs to be kicked down to 2.5GT.

Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
parent e5a06939

arch/tile/Kconfig

+12 −0
Original line number Diff line number Diff line
@@ -329,6 +329,18 @@ endmenu # Tilera-specific configuration 


menu "Bus options"



config PCI

	bool "PCI support"

	default y

	select PCI_DOMAINS

	---help---

	  Enable PCI root complex support, so PCIe endpoint devices can

	  be attached to the Tile chip.  Many, but not all, PCI devices

	  are supported under Tilera's root complex driver.



config PCI_DOMAINS

	bool



config NO_IOMEM

	def_bool !PCI

arch/tile/include/asm/io.h

+11 −4
Original line number Diff line number Diff line
@@ -55,9 +55,6 @@ extern void iounmap(volatile void __iomem *addr); 
#define ioremap_writethrough(physaddr, size)	ioremap(physaddr, size)

#define ioremap_fullcache(physaddr, size)	ioremap(physaddr, size)



void __iomem *ioport_map(unsigned long port, unsigned int len);

extern inline void ioport_unmap(void __iomem *addr) {}



#define mmiowb()



/* Conversion between virtual and physical mappings.  */
@@ -189,12 +186,22 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, 
 * we never run, uses them unconditionally.

 */



static inline int ioport_panic(void)

static inline long ioport_panic(void)

{

	panic("inb/outb and friends do not exist on tile");

	return 0;

}



static inline void __iomem *ioport_map(unsigned long port, unsigned int len)

{

	return (void __iomem *) ioport_panic();

}



static inline void ioport_unmap(void __iomem *addr)

{

	ioport_panic();

}



static inline u8 inb(unsigned long addr)

{

	return ioport_panic();

arch/tile/include/asm/pci-bridge.h

deleted100644 → 0
+0 −117
Original line number Diff line number Diff line 
/*

 * Copyright 2010 Tilera Corporation. All Rights Reserved.

 *

 *   This program is free software; you can redistribute it and/or

 *   modify it under the terms of the GNU General Public License

 *   as published by the Free Software Foundation, version 2.

 *

 *   This program is distributed in the hope that it will be useful, but

 *   WITHOUT ANY WARRANTY; without even the implied warranty of

 *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or

 *   NON INFRINGEMENT.  See the GNU General Public License for

 *   more details.

 */



#ifndef _ASM_TILE_PCI_BRIDGE_H

#define _ASM_TILE_PCI_BRIDGE_H



#include <linux/ioport.h>

#include <linux/pci.h>



struct device_node;

struct pci_controller;



/*

 * pci_io_base returns the memory address at which you can access

 * the I/O space for PCI bus number `bus' (or NULL on error).

 */

extern void __iomem *pci_bus_io_base(unsigned int bus);

extern unsigned long pci_bus_io_base_phys(unsigned int bus);

extern unsigned long pci_bus_mem_base_phys(unsigned int bus);



/* Allocate a new PCI host bridge structure */

extern struct pci_controller *pcibios_alloc_controller(void);



/* Helper function for setting up resources */

extern void pci_init_resource(struct resource *res, unsigned long start,

			      unsigned long end, int flags, char *name);



/* Get the PCI host controller for a bus */

extern struct pci_controller *pci_bus_to_hose(int bus);



/*

 * Structure of a PCI controller (host bridge)

 */

struct pci_controller {

	int index;		/* PCI domain number */

	struct pci_bus *root_bus;



	int first_busno;

	int last_busno;



	int hv_cfg_fd[2];	/* config{0,1} fds for this PCIe controller */

	int hv_mem_fd;		/* fd to Hypervisor for MMIO operations */



	struct pci_ops *ops;



	int irq_base;		/* Base IRQ from the Hypervisor	*/

	int plx_gen1;		/* flag for PLX Gen 1 configuration */



	/* Address ranges that are routed to this controller/bridge. */

	struct resource mem_resources[3];

};



static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)

{

	return bus->sysdata;

}



extern void setup_indirect_pci_nomap(struct pci_controller *hose,

			       void __iomem *cfg_addr, void __iomem *cfg_data);

extern void setup_indirect_pci(struct pci_controller *hose,

			       u32 cfg_addr, u32 cfg_data);

extern void setup_grackle(struct pci_controller *hose);



extern unsigned char common_swizzle(struct pci_dev *, unsigned char *);



/*

 *   The following code swizzles for exactly one bridge.  The routine

 *   common_swizzle below handles multiple bridges.  But there are a

 *   some boards that don't follow the PCI spec's suggestion so we

 *   break this piece out separately.

 */

static inline unsigned char bridge_swizzle(unsigned char pin,

		unsigned char idsel)

{

	return (((pin-1) + idsel) % 4) + 1;

}



/*

 * The following macro is used to lookup irqs in a standard table

 * format for those PPC systems that do not already have PCI

 * interrupts properly routed.

 */

/* FIXME - double check this */

#define PCI_IRQ_TABLE_LOOKUP ({ \

	long _ctl_ = -1; \

	if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \

		_ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \

	_ctl_; \

})



/*

 * Scan the buses below a given PCI host bridge and assign suitable

 * resources to all devices found.

 */

extern int pciauto_bus_scan(struct pci_controller *, int);



#ifdef CONFIG_PCI

extern unsigned long pci_address_to_pio(phys_addr_t address);

#else

static inline unsigned long pci_address_to_pio(phys_addr_t address)

{

	return (unsigned long)-1;

}

#endif



#endif /* _ASM_TILE_PCI_BRIDGE_H */

arch/tile/include/asm/pci.h

+41 −66
Original line number Diff line number Diff line
@@ -15,7 +15,29 @@ 
#ifndef _ASM_TILE_PCI_H

#define _ASM_TILE_PCI_H



#include <asm/pci-bridge.h>

#include <linux/pci.h>



/*

 * Structure of a PCI controller (host bridge)

 */

struct pci_controller {

	int index;		/* PCI domain number */

	struct pci_bus *root_bus;



	int first_busno;

	int last_busno;



	int hv_cfg_fd[2];	/* config{0,1} fds for this PCIe controller */

	int hv_mem_fd;		/* fd to Hypervisor for MMIO operations */



	struct pci_ops *ops;



	int irq_base;		/* Base IRQ from the Hypervisor	*/

	int plx_gen1;		/* flag for PLX Gen 1 configuration */



	/* Address ranges that are routed to this controller/bridge. */

	struct resource mem_resources[3];

};



/*

 * The hypervisor maps the entirety of CPA-space as bus addresses, so
@@ -24,56 +46,12 @@ 
 */

#define PCI_DMA_BUS_IS_PHYS     1



struct pci_controller *pci_bus_to_hose(int bus);

unsigned char __init common_swizzle(struct pci_dev *dev, unsigned char *pinp);

int __init tile_pci_init(void);

void pci_iounmap(struct pci_dev *dev, void __iomem *addr);

void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);

void __devinit pcibios_fixup_bus(struct pci_bus *bus);



int __devinit _tile_cfg_read(struct pci_controller *hose,

				    int bus,

				    int slot,

				    int function,

				    int offset,

				    int size,

				    u32 *val);

int __devinit _tile_cfg_write(struct pci_controller *hose,

				     int bus,

				     int slot,

				     int function,

				     int offset,

				     int size,

				     u32 val);

void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);

static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}



/*

 * These are used to to config reads and writes in the early stages of

 * setup before the driver infrastructure has been set up enough to be

 * able to do config reads and writes.

 */

#define early_cfg_read(where, size, value) \

	_tile_cfg_read(controller, \

		       current_bus, \

		       pci_slot, \

		       pci_fn, \

		       where, \

		       size, \

		       value)



#define early_cfg_write(where, size, value) \

	_tile_cfg_write(controller, \

		       current_bus, \

		       pci_slot, \

		       pci_fn, \

		       where, \

		       size, \

		       value)







#define PCICFG_BYTE	1

#define PCICFG_WORD	2

#define PCICFG_DWORD	4

void __devinit pcibios_fixup_bus(struct pci_bus *bus);



#define	TILE_NUM_PCIE	2
@@ -88,33 +66,33 @@ static inline int pci_proc_domain(struct pci_bus *bus) 
}



/*

 * I/O space is currently not supported.

 * pcibios_assign_all_busses() tells whether or not the bus numbers

 * should be reassigned, in case the BIOS didn't do it correctly, or

 * in case we don't have a BIOS and we want to let Linux do it.

 */

static inline int pcibios_assign_all_busses(void)

{

	return 1;

}



#define TILE_PCIE_LOWER_IO		0x0

#define TILE_PCIE_UPPER_IO		0x10000

#define TILE_PCIE_PCIE_IO_SIZE		0x0000FFFF



#define _PAGE_NO_CACHE		0

#define _PAGE_GUARDED		0





#define pcibios_assign_all_busses()    pci_assign_all_buses

extern int pci_assign_all_buses;



/*

 * No special bus mastering setup handling.

 */

static inline void pcibios_set_master(struct pci_dev *dev)

{

	/* No special bus mastering setup handling */

}



#define PCIBIOS_MIN_MEM		0

#define PCIBIOS_MIN_IO		TILE_PCIE_LOWER_IO

#define PCIBIOS_MIN_IO		0



/*

 * This flag tells if the platform is TILEmpower that needs

 * special configuration for the PLX switch chip.

 */

extern int blade_pci;

extern int tile_plx_gen1;



/* Use any cpu for PCI. */

#define cpumask_of_pcibus(bus) cpu_online_mask



/* implement the pci_ DMA API in terms of the generic device dma_ one */

#include <asm-generic/pci-dma-compat.h>
@@ -122,7 +100,4 @@ extern int blade_pci; 
/* generic pci stuff */

#include <asm-generic/pci.h>



/* Use any cpu for PCI. */

#define cpumask_of_pcibus(bus) cpu_online_mask



#endif /* _ASM_TILE_PCI_H */

arch/tile/kernel/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -15,3 +15,4 @@ obj-$(CONFIG_SMP) += smpboot.o smp.o tlb.o 
obj-$(CONFIG_MODULES)		+= module.o

obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o

obj-$(CONFIG_KEXEC)		+= machine_kexec.o relocate_kernel.o

obj-$(CONFIG_PCI)		+= pci.o

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