Commit f0210518 authored by Chunfeng Yun's avatar Chunfeng Yun Committed by Matthias Brugger
Browse files

arm64: dts: mt2712: use non-empty ranges for usb-phy 



Use non-empty ranges for usb-phy to make the layout of
its registers clearer;
Replace deprecated compatible by generic

Signed-off-by: default avatarChunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent fff12573

arch/arm64/boot/dts/mediatek/mt2712e.dtsi

+22 −20
Original line number Diff line number Diff line
@@ -703,30 +703,31 @@ 
	};



	u3phy0: usb-phy@11290000 {

		compatible = "mediatek,mt2712-u3phy";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;

		compatible = "mediatek,mt2712-tphy",

			     "mediatek,generic-tphy-v2";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0 0x11290000 0x9000>;

		status = "okay";



		u2port0: usb-phy@11290000 {

			reg = <0 0x11290000 0 0x700>;

		u2port0: usb-phy@0 {

			reg = <0x0 0x700>;

			clocks = <&clk26m>;

			clock-names = "ref";

			#phy-cells = <1>;

			status = "okay";

		};



		u2port1: usb-phy@11298000 {

			reg = <0 0x11298000 0 0x700>;

		u2port1: usb-phy@8000 {

			reg = <0x8000 0x700>;

			clocks = <&clk26m>;

			clock-names = "ref";

			#phy-cells = <1>;

			status = "okay";

		};



		u3port0: usb-phy@11298700 {

			reg = <0 0x11298700 0 0x900>;

		u3port0: usb-phy@8700 {

			reg = <0x8700 0x900>;

			clocks = <&clk26m>;

			clock-names = "ref";

			#phy-cells = <1>;
@@ -766,30 +767,31 @@ 
	};



	u3phy1: usb-phy@112e0000 {

		compatible = "mediatek,mt2712-u3phy";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;

		compatible = "mediatek,mt2712-tphy",

			     "mediatek,generic-tphy-v2";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0 0x112e0000 0x9000>;

		status = "okay";



		u2port2: usb-phy@112e0000 {

			reg = <0 0x112e0000 0 0x700>;

		u2port2: usb-phy@0 {

			reg = <0x0 0x700>;

			clocks = <&clk26m>;

			clock-names = "ref";

			#phy-cells = <1>;

			status = "okay";

		};



		u2port3: usb-phy@112e8000 {

			reg = <0 0x112e8000 0 0x700>;

		u2port3: usb-phy@8000 {

			reg = <0x8000 0x700>;

			clocks = <&clk26m>;

			clock-names = "ref";

			#phy-cells = <1>;

			status = "okay";

		};



		u3port1: usb-phy@112e8700 {

			reg = <0 0x112e8700 0 0x900>;

		u3port1: usb-phy@8700 {

			reg = <0x8700 0x900>;

			clocks = <&clk26m>;

			clock-names = "ref";

			#phy-cells = <1>;

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