Commit f0157160 authored by Keith Busch's avatar Keith Busch Committed by Bjorn Helgaas
Browse files

PCI: Make link active reporting detection generic 



The spec has timing requirements when waiting for a link to become active
after a conventional reset.  Implement those hard delays when waiting for
an active link so pciehp and dpc drivers don't need to duplicate this.

For devices that don't support data link layer active reporting, wait the
fixed time recommended by the PCIe spec.

Signed-off-by: default avatarKeith Busch <keith.busch@intel.com>
[bhelgaas: changelog]
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarSinan Kaya <okaya@kernel.org>
parent a6bd101b

drivers/pci/hotplug/pciehp.h

+0 −6
Original line number Diff line number Diff line
@@ -62,11 +62,6 @@ do { \ 
 * struct controller - PCIe hotplug controller

 * @pcie: pointer to the controller's PCIe port service device

 * @slot_cap: cached copy of the Slot Capabilities register

 * @link_active_reporting: cached copy of Data Link Layer Link Active Reporting

 *	Capable bit in Link Capabilities register; if this bit is zero, the

 *	Data Link Layer Link Active bit in the Link Status register will never

 *	be set and the driver is thus confined to wait 1 second before assuming

 *	the link to a hotplugged device is up and accessing it

 * @slot_ctrl: cached copy of the Slot Control register

 * @ctrl_lock: serializes writes to the Slot Control register

 * @cmd_started: jiffies when the Slot Control register was last written;
@@ -103,7 +98,6 @@ struct controller { 
	struct pcie_device *pcie;



	u32 slot_cap;				/* capabilities and quirks */

	unsigned int link_active_reporting:1;



	u16 slot_ctrl;				/* control register access */

	struct mutex ctrl_lock;

drivers/pci/hotplug/pciehp_hpc.c

+2 −20
Original line number Diff line number Diff line
@@ -214,13 +214,6 @@ bool pciehp_check_link_active(struct controller *ctrl) 
	return ret;

}



static void pcie_wait_link_active(struct controller *ctrl)

{

	struct pci_dev *pdev = ctrl_dev(ctrl);



	pcie_wait_for_link(pdev, true);

}



static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)

{

	u32 l;
@@ -253,18 +246,9 @@ int pciehp_check_link_status(struct controller *ctrl) 
	bool found;

	u16 lnk_status;



	/*

	 * Data Link Layer Link Active Reporting must be capable for

	 * hot-plug capable downstream port. But old controller might

	 * not implement it. In this case, we wait for 1000 ms.

	*/

	if (ctrl->link_active_reporting)

		pcie_wait_link_active(ctrl);

	else

		msleep(1000);

	if (!pcie_wait_for_link(pdev, true))

		return -1;



	/* wait 100ms before read pci conf, and try in 1s */

	msleep(100);

	found = pci_bus_check_dev(ctrl->pcie->port->subordinate,

					PCI_DEVFN(0, 0));
@@ -865,8 +849,6 @@ struct controller *pcie_init(struct pcie_device *dev) 


	/* Check if Data Link Layer Link Active Reporting is implemented */

	pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);

	if (link_cap & PCI_EXP_LNKCAP_DLLLARC)

		ctrl->link_active_reporting = 1;



	/* Clear all remaining event bits in Slot Status register. */

	pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,

drivers/pci/pci.c

+27 −6
Original line number Diff line number Diff line
@@ -4489,21 +4489,42 @@ bool pcie_wait_for_link(struct pci_dev *pdev, bool active) 
	bool ret;

	u16 lnk_status;



	/*

	 * Some controllers might not implement link active reporting. In this

	 * case, we wait for 1000 + 100 ms.

	 */

	if (!pdev->link_active_reporting) {

		msleep(1100);

		return true;

	}



	/*

	 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,

	 * after which we should expect an link active if the reset was

	 * successful. If so, software must wait a minimum 100ms before sending

	 * configuration requests to devices downstream this port.

	 *

	 * If the link fails to activate, either the device was physically

	 * removed or the link is permanently failed.

	 */

	if (active)

		msleep(20);

	for (;;) {

		pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);

		ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);

		if (ret == active)

			return true;

			break;

		if (timeout <= 0)

			break;

		msleep(10);

		timeout -= 10;

	}



	if (active && ret)

		msleep(100);

	else if (ret != active)

		pci_info(pdev, "Data Link Layer Link Active not %s in 1000 msec\n",

			active ? "set" : "cleared");



	return false;

	return ret == active;

}



void pci_reset_secondary_bus(struct pci_dev *dev)

drivers/pci/pcie/dpc.c

+3 −1
Original line number Diff line number Diff line
@@ -140,10 +140,12 @@ static pci_ers_result_t dpc_reset_link(struct pci_dev *pdev) 
	pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,

			      PCI_EXP_DPC_STATUS_TRIGGER);



	if (!pcie_wait_for_link(pdev, true))

		return PCI_ERS_RESULT_DISCONNECT;



	return PCI_ERS_RESULT_RECOVERED;

}





static void dpc_process_rp_pio_error(struct dpc_dev *dpc)

{

	struct device *dev = &dpc->dev->device;

drivers/pci/probe.c

+1 −0
Original line number Diff line number Diff line
@@ -713,6 +713,7 @@ static void pci_set_bus_speed(struct pci_bus *bus) 


		pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);

		bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];

		bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC);



		pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);

		pcie_update_link_speed(bus, linksta);

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