Commit f013820f authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'cxgb4-hw-debug-logs' 



Rahul Lakkireddy says:

====================
cxgb4: add support to get hardware debug logs via ethtool

This series of patches add support to collect hardware debug logs
via ethtool --get-dump facility.

Currently supports:

Memory dumps - Collects on-chip EDC0 and EDC1 dumps.
Hardware dumps - Collects firmware and hardware dumps.

Patch 1 adds ethtool set/get dump data.  It also adds template header
that precedes dump data.  This template header gives additional
information needed for extracting and decoding the collected dump
data.

Patch 2 adds base to collect dumps.  Also collects regdump.

Patch 3 collects on-chip EDC0 and EDC1 memory dumps.

Patch 4 collects firmware mbox log and device log.

Patch 5 updates base API for accessing TP indirect registers.

Patch 6 collects hardware TP module dump.

Patch 7 collects hardware SGE, PCIE, PM, UP CIM, MA, and HMA
module dumps.

Patch 8 collects hardware IBQ and OBQ dump.

Thanks,
Rahul

---
v2:
- Prefix symbols that pollute global namespace in files starting
  with cxgb4_* with "cxgb4_"
- Prefix symbols that pollute global namespace in files starting
  with cudbg_* with "cudbg_"
- Make cudbg_collect_mem_info() static.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 4c7787ba 7c075ce2

drivers/net/ethernet/chelsio/cxgb4/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -6,7 +6,8 @@ obj-$(CONFIG_CHELSIO_T4) += cxgb4.o 


cxgb4-objs := cxgb4_main.o l2t.o t4_hw.o sge.o clip_tbl.o cxgb4_ethtool.o \

	      cxgb4_uld.o sched.o cxgb4_filter.o cxgb4_tc_u32.o \

	      cxgb4_ptp.o cxgb4_tc_flower.o

	      cxgb4_ptp.o cxgb4_tc_flower.o cxgb4_cudbg.o \

	      cudbg_common.o cudbg_lib.o

cxgb4-$(CONFIG_CHELSIO_T4_DCB) +=  cxgb4_dcb.o

cxgb4-$(CONFIG_CHELSIO_T4_FCOE) +=  cxgb4_fcoe.o

cxgb4-$(CONFIG_DEBUG_FS) += cxgb4_debugfs.o

drivers/net/ethernet/chelsio/cxgb4/cudbg_common.c

0 → 100644
+54 −0
Original line number Diff line number Diff line 
/*

 *  Copyright (C) 2017 Chelsio Communications.  All rights reserved.

 *

 *  This program is free software; you can redistribute it and/or modify it

 *  under the terms and conditions of the GNU General Public License,

 *  version 2, as published by the Free Software Foundation.

 *

 *  This program is distributed in the hope it will be useful, but WITHOUT

 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 *  more details.

 *

 *  The full GNU General Public License is included in this distribution in

 *  the file called "COPYING".

 *

 */



#include "cxgb4.h"

#include "cudbg_if.h"

#include "cudbg_lib_common.h"



int cudbg_get_buff(struct cudbg_buffer *pdbg_buff, u32 size,

		   struct cudbg_buffer *pin_buff)

{

	u32 offset;



	offset = pdbg_buff->offset;

	if (offset + size > pdbg_buff->size)

		return CUDBG_STATUS_NO_MEM;



	pin_buff->data = (char *)pdbg_buff->data + offset;

	pin_buff->offset = offset;

	pin_buff->size = size;

	pdbg_buff->size -= size;

	return 0;

}



void cudbg_put_buff(struct cudbg_buffer *pin_buff,

		    struct cudbg_buffer *pdbg_buff)

{

	pdbg_buff->size += pin_buff->size;

	pin_buff->data = NULL;

	pin_buff->offset = 0;

	pin_buff->size = 0;

}



void cudbg_update_buff(struct cudbg_buffer *pin_buff,

		       struct cudbg_buffer *pout_buff)

{

	/* We already write to buffer provided by ethool, so just

	 * increment offset to next free space.

	 */

	pout_buff->offset += pin_buff->size;

}

drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h

0 → 100644
+181 −0
Original line number Diff line number Diff line 
/*

 *  Copyright (C) 2017 Chelsio Communications.  All rights reserved.

 *

 *  This program is free software; you can redistribute it and/or modify it

 *  under the terms and conditions of the GNU General Public License,

 *  version 2, as published by the Free Software Foundation.

 *

 *  This program is distributed in the hope it will be useful, but WITHOUT

 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 *  more details.

 *

 *  The full GNU General Public License is included in this distribution in

 *  the file called "COPYING".

 *

 */



#ifndef __CUDBG_ENTITY_H__

#define __CUDBG_ENTITY_H__



#define EDC0_FLAG 3

#define EDC1_FLAG 4



struct card_mem {

	u16 size_edc0;

	u16 size_edc1;

	u16 mem_flag;

};



struct cudbg_mbox_log {

	struct mbox_cmd entry;

	u32 hi[MBOX_LEN / 8];

	u32 lo[MBOX_LEN / 8];

};



struct ireg_field {

	u32 ireg_addr;

	u32 ireg_data;

	u32 ireg_local_offset;

	u32 ireg_offset_range;

};



struct ireg_buf {

	struct ireg_field tp_pio;

	u32 outbuf[32];

};



#define IREG_NUM_ELEM 4



static const u32 t6_tp_pio_array[][IREG_NUM_ELEM] = {

	{0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */

	{0x7e40, 0x7e44, 0x040, 10}, /* t6_tp_pio_regs_40_to_49 */

	{0x7e40, 0x7e44, 0x050, 10}, /* t6_tp_pio_regs_50_to_59 */

	{0x7e40, 0x7e44, 0x060, 14}, /* t6_tp_pio_regs_60_to_6d */

	{0x7e40, 0x7e44, 0x06F, 1}, /* t6_tp_pio_regs_6f */

	{0x7e40, 0x7e44, 0x070, 6}, /* t6_tp_pio_regs_70_to_75 */

	{0x7e40, 0x7e44, 0x130, 18}, /* t6_tp_pio_regs_130_to_141 */

	{0x7e40, 0x7e44, 0x145, 19}, /* t6_tp_pio_regs_145_to_157 */

	{0x7e40, 0x7e44, 0x160, 1}, /* t6_tp_pio_regs_160 */

	{0x7e40, 0x7e44, 0x230, 25}, /* t6_tp_pio_regs_230_to_248 */

	{0x7e40, 0x7e44, 0x24a, 3}, /* t6_tp_pio_regs_24c */

	{0x7e40, 0x7e44, 0x8C0, 1} /* t6_tp_pio_regs_8c0 */

};



static const u32 t5_tp_pio_array[][IREG_NUM_ELEM] = {

	{0x7e40, 0x7e44, 0x020, 28}, /* t5_tp_pio_regs_20_to_3b */

	{0x7e40, 0x7e44, 0x040, 19}, /* t5_tp_pio_regs_40_to_52 */

	{0x7e40, 0x7e44, 0x054, 2}, /* t5_tp_pio_regs_54_to_55 */

	{0x7e40, 0x7e44, 0x060, 13}, /* t5_tp_pio_regs_60_to_6c */

	{0x7e40, 0x7e44, 0x06F, 1}, /* t5_tp_pio_regs_6f */

	{0x7e40, 0x7e44, 0x120, 4}, /* t5_tp_pio_regs_120_to_123 */

	{0x7e40, 0x7e44, 0x12b, 2}, /* t5_tp_pio_regs_12b_to_12c */

	{0x7e40, 0x7e44, 0x12f, 21}, /* t5_tp_pio_regs_12f_to_143 */

	{0x7e40, 0x7e44, 0x145, 19}, /* t5_tp_pio_regs_145_to_157 */

	{0x7e40, 0x7e44, 0x230, 25}, /* t5_tp_pio_regs_230_to_248 */

	{0x7e40, 0x7e44, 0x8C0, 1} /* t5_tp_pio_regs_8c0 */

};



static const u32 t6_tp_tm_pio_array[][IREG_NUM_ELEM] = {

	{0x7e18, 0x7e1c, 0x0, 12}

};



static const u32 t5_tp_tm_pio_array[][IREG_NUM_ELEM] = {

	{0x7e18, 0x7e1c, 0x0, 12}

};



static const u32 t6_tp_mib_index_array[6][IREG_NUM_ELEM] = {

	{0x7e50, 0x7e54, 0x0, 13},

	{0x7e50, 0x7e54, 0x10, 6},

	{0x7e50, 0x7e54, 0x18, 21},

	{0x7e50, 0x7e54, 0x30, 32},

	{0x7e50, 0x7e54, 0x50, 22},

	{0x7e50, 0x7e54, 0x68, 12}

};



static const u32 t5_tp_mib_index_array[9][IREG_NUM_ELEM] = {

	{0x7e50, 0x7e54, 0x0, 13},

	{0x7e50, 0x7e54, 0x10, 6},

	{0x7e50, 0x7e54, 0x18, 8},

	{0x7e50, 0x7e54, 0x20, 13},

	{0x7e50, 0x7e54, 0x30, 16},

	{0x7e50, 0x7e54, 0x40, 16},

	{0x7e50, 0x7e54, 0x50, 16},

	{0x7e50, 0x7e54, 0x60, 6},

	{0x7e50, 0x7e54, 0x68, 4}

};



static const u32 t5_sge_dbg_index_array[2][IREG_NUM_ELEM] = {

	{0x10cc, 0x10d0, 0x0, 16},

	{0x10cc, 0x10d4, 0x0, 16},

};



static const u32 t5_pcie_pdbg_array[][IREG_NUM_ELEM] = {

	{0x5a04, 0x5a0c, 0x00, 0x20}, /* t5_pcie_pdbg_regs_00_to_20 */

	{0x5a04, 0x5a0c, 0x21, 0x20}, /* t5_pcie_pdbg_regs_21_to_40 */

	{0x5a04, 0x5a0c, 0x41, 0x10}, /* t5_pcie_pdbg_regs_41_to_50 */

};



static const u32 t5_pcie_cdbg_array[][IREG_NUM_ELEM] = {

	{0x5a10, 0x5a18, 0x00, 0x20}, /* t5_pcie_cdbg_regs_00_to_20 */

	{0x5a10, 0x5a18, 0x21, 0x18}, /* t5_pcie_cdbg_regs_21_to_37 */

};



static const u32 t5_pm_rx_array[][IREG_NUM_ELEM] = {

	{0x8FD0, 0x8FD4, 0x10000, 0x20}, /* t5_pm_rx_regs_10000_to_10020 */

	{0x8FD0, 0x8FD4, 0x10021, 0x0D}, /* t5_pm_rx_regs_10021_to_1002c */

};



static const u32 t5_pm_tx_array[][IREG_NUM_ELEM] = {

	{0x8FF0, 0x8FF4, 0x10000, 0x20}, /* t5_pm_tx_regs_10000_to_10020 */

	{0x8FF0, 0x8FF4, 0x10021, 0x1D}, /* t5_pm_tx_regs_10021_to_1003c */

};



static const u32 t6_ma_ireg_array[][IREG_NUM_ELEM] = {

	{0x78f8, 0x78fc, 0xa000, 23}, /* t6_ma_regs_a000_to_a016 */

	{0x78f8, 0x78fc, 0xa400, 30}, /* t6_ma_regs_a400_to_a41e */

	{0x78f8, 0x78fc, 0xa800, 20} /* t6_ma_regs_a800_to_a813 */

};



static const u32 t6_ma_ireg_array2[][IREG_NUM_ELEM] = {

	{0x78f8, 0x78fc, 0xe400, 17}, /* t6_ma_regs_e400_to_e600 */

	{0x78f8, 0x78fc, 0xe640, 13} /* t6_ma_regs_e640_to_e7c0 */

};



static const u32 t6_up_cim_reg_array[][IREG_NUM_ELEM] = {

	{0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */

	{0x7b50, 0x7b54, 0x2080, 0x1d}, /* up_cim_2080_to_20fc */

	{0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */

	{0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */

	{0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */

	{0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */

	{0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */

	{0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */

	{0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */

	{0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */

	{0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */

	{0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */

	{0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */



};



static const u32 t5_up_cim_reg_array[][IREG_NUM_ELEM] = {

	{0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */

	{0x7b50, 0x7b54, 0x2080, 0x19}, /* up_cim_2080_to_20ec */

	{0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */

	{0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */

	{0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */

	{0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */

	{0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */

	{0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */

	{0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */

	{0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */

	{0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */

	{0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */

	{0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */

};



static const u32 t6_hma_ireg_array[][IREG_NUM_ELEM] = {

	{0x51320, 0x51324, 0xa000, 32} /* t6_hma_regs_a000_to_a01f */

};

#endif /* __CUDBG_ENTITY_H__ */

drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h

0 → 100644
+69 −0
Original line number Diff line number Diff line 
/*

 *  Copyright (C) 2017 Chelsio Communications.  All rights reserved.

 *

 *  This program is free software; you can redistribute it and/or modify it

 *  under the terms and conditions of the GNU General Public License,

 *  version 2, as published by the Free Software Foundation.

 *

 *  This program is distributed in the hope it will be useful, but WITHOUT

 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 *  more details.

 *

 *  The full GNU General Public License is included in this distribution in

 *  the file called "COPYING".

 *

 */



#ifndef __CUDBG_IF_H__

#define __CUDBG_IF_H__



/* Error codes */

#define CUDBG_STATUS_NO_MEM -19

#define CUDBG_STATUS_ENTITY_NOT_FOUND -24

#define CUDBG_SYSTEM_ERROR -29



#define CUDBG_MAJOR_VERSION 1

#define CUDBG_MINOR_VERSION 14



enum cudbg_dbg_entity_type {

	CUDBG_REG_DUMP = 1,

	CUDBG_DEV_LOG = 2,

	CUDBG_CIM_IBQ_TP0 = 6,

	CUDBG_CIM_IBQ_TP1 = 7,

	CUDBG_CIM_IBQ_ULP = 8,

	CUDBG_CIM_IBQ_SGE0 = 9,

	CUDBG_CIM_IBQ_SGE1 = 10,

	CUDBG_CIM_IBQ_NCSI = 11,

	CUDBG_CIM_OBQ_ULP0 = 12,

	CUDBG_CIM_OBQ_ULP1 = 13,

	CUDBG_CIM_OBQ_ULP2 = 14,

	CUDBG_CIM_OBQ_ULP3 = 15,

	CUDBG_CIM_OBQ_SGE = 16,

	CUDBG_CIM_OBQ_NCSI = 17,

	CUDBG_EDC0 = 18,

	CUDBG_EDC1 = 19,

	CUDBG_TP_INDIRECT = 36,

	CUDBG_SGE_INDIRECT = 37,

	CUDBG_CIM_OBQ_RXQ0 = 47,

	CUDBG_CIM_OBQ_RXQ1 = 48,

	CUDBG_PCIE_INDIRECT = 50,

	CUDBG_PM_INDIRECT = 51,

	CUDBG_MA_INDIRECT = 61,

	CUDBG_UP_CIM_INDIRECT = 64,

	CUDBG_MBOX_LOG = 66,

	CUDBG_HMA_INDIRECT = 67,

	CUDBG_MAX_ENTITY = 70,

};



struct cudbg_init {

	struct adapter *adap; /* Pointer to adapter structure */

	void *outbuf; /* Output buffer */

	u32 outbuf_size;  /* Output buffer size */

};



static inline unsigned int cudbg_mbytes_to_bytes(unsigned int size)

{

	return size * 1024 * 1024;

}

#endif /* __CUDBG_IF_H__ */

drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c

0 → 100644
+867 −0

File added.

Preview size limit exceeded, changes collapsed.

CRA Git | Maintained and supported by SUSTech CRA and CCSE