Commit f00889dc authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Allow PState switch in VBLANK one display VACTIVE 



[Why]
For certain display configurations we want to allow PSTATE
switch when one display can switch in VACTIVE and the
other display can switch in VBLANK

[How]
Add extra condition to dcn2 pstate support check

Signed-off-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5f6dbd54

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -476,6 +476,7 @@ struct dc_debug_options { 
	bool enable_dmcub_surface_flip;

	bool usbc_combo_phy_reset_wa;

	bool disable_dsc;

	bool enable_dram_clock_change_one_display_vactive;

};



struct dc_debug_data {

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+2 −0
Original line number Diff line number Diff line
@@ -3112,6 +3112,8 @@ static noinline bool dcn20_validate_bandwidth_fp(struct dc *dc, 
	p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;

	context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =

		dc->debug.disable_dram_clock_change_vactive_support;

	context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive =

		dc->debug.enable_dram_clock_change_one_display_vactive;



	if (fast_validate) {

		return dcn20_validate_bandwidth_internal(dc, context, true);

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

+28 −1
Original line number Diff line number Diff line
@@ -2599,18 +2599,40 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP 
		}

	}



	{

	float SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = 999999;

	int PlaneWithMinActiveDRAMClockChangeMargin = -1;



	mode_lib->vba.MinActiveDRAMClockChangeMargin = 999999;

	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {

		if (mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]

				< mode_lib->vba.MinActiveDRAMClockChangeMargin) {

			mode_lib->vba.MinActiveDRAMClockChangeMargin =

					mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];

			if (mode_lib->vba.BlendingAndTiming[k] == k) {

				PlaneWithMinActiveDRAMClockChangeMargin = k;

			} else {

				for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) {

					if (mode_lib->vba.BlendingAndTiming[k] == j) {

						PlaneWithMinActiveDRAMClockChangeMargin = j;

					}

				}

			}

		}

	}



	mode_lib->vba.MinActiveDRAMClockChangeLatencySupported =

			mode_lib->vba.MinActiveDRAMClockChangeMargin

					+ mode_lib->vba.DRAMClockChangeLatency;

	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {

		if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (mode_lib->vba.BlendingAndTiming[k] == k))

				&& !(mode_lib->vba.BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin)

				&& mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]

						< SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) {

			SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank =

					mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];

		}

	}



	if (mode_lib->vba.DRAMClockChangeSupportsVActive &&

			mode_lib->vba.MinActiveDRAMClockChangeMargin > 60) {
@@ -2629,7 +2651,11 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP 
			mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {

		mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;

	} else {

		if (mode_lib->vba.SynchronizedVBlank || mode_lib->vba.NumberOfActivePlanes == 1) {

		if ((mode_lib->vba.SynchronizedVBlank

				|| mode_lib->vba.NumberOfActivePlanes == 1

				|| (SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank > 0 &&

						mode_lib->vba.AllowDramClockChangeOneDisplayVactive))

					&& mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) {

			mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vblank;

			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {

				if (!mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k]) {
@@ -2641,6 +2667,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP 
			mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_unsupported;

		}

	}

	}

	for (k = 0; k <= mode_lib->vba.soc.num_states; k++)

		for (j = 0; j < 2; j++)

			mode_lib->vba.DRAMClockChangeSupport[k][j] = mode_lib->vba.DRAMClockChangeSupport[0][0];

drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h

+1 −0
Original line number Diff line number Diff line
@@ -118,6 +118,7 @@ struct _vcs_dpi_soc_bounding_box_st { 
	double urgent_latency_adjustment_fabric_clock_component_us;

	double urgent_latency_adjustment_fabric_clock_reference_mhz;

	bool disable_dram_clock_change_vactive_support;

	bool allow_dram_clock_one_display_vactive;

};



struct _vcs_dpi_ip_params_st {

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c

+1 −0
Original line number Diff line number Diff line
@@ -224,6 +224,7 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib) 
	mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us;

	mode_lib->vba.DRAMClockChangeSupportsVActive = !soc->disable_dram_clock_change_vactive_support ||

			mode_lib->vba.DummyPStateCheck;

	mode_lib->vba.AllowDramClockChangeOneDisplayVactive = soc->allow_dram_clock_one_display_vactive;



	mode_lib->vba.Downspreading = soc->downspread_percent;

	mode_lib->vba.DRAMChannelWidth = soc->dram_channel_width_bytes;   // new!

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