Commit efc351b1 authored May 08, 2018 by Dmitry Osipenko Committed by Thierry Reding May 18, 2018

clk: tegra20: Correct parents of CDEV1/2 clocks



Parents of CDEV1/2 clocks are determined by muxing of the corresponding
pins. Pinctrl driver now provides the CDEV1/2 clock muxes and hence
CDEV1/2 clocks could have correct parents. Set CDEV1/2 parents to the
corresponding muxes to fix the parents.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Marc Dietrich <marvin24@gmx.de>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

parent 08a52593

drivers/clk/tegra/clk-tegra20.c

+2 −4

Original line number	Diff line number	Diff line
		@@ -846,14 +846,12 @@ static void __init tegra20_periph_clk_init(void)
		NULL);

		/* cdev1 */
		clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, 0, 26000000);
		clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0,
		clk = tegra_clk_register_periph_gate("cdev1", "cdev1_mux", 0,
		clk_base, 0, 94, periph_clk_enb_refcnt);
		clks[TEGRA20_CLK_CDEV1] = clk;

		/* cdev2 */
		clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, 0, 26000000);
		clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0,
		clk = tegra_clk_register_periph_gate("cdev2", "cdev2_mux", 0,
		clk_base, 0, 93, periph_clk_enb_refcnt);
		clks[TEGRA20_CLK_CDEV2] = clk;

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