Commit efbd9129 authored by Taniya Das's avatar Taniya Das Committed by Stephen Boyd
Browse files

clk: qcom: dispcc: Remove support of disp_cc_mdss_rscc_ahb_clk 



The disp_cc_mdss_rscc_ahb_clk is default enabled from hardware and thus
does not require to be marked CRITICAL. This which would allow the RCG to
be turned OFF when the display turns OFF and not blocking XO.

Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1581423236-21341-2-git-send-email-tdas@codeaurora.org


Fixes: dd3d0662 ("clk: qcom: Add display clock controller driver for SC7180")
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 8de427d5

drivers/clk/qcom/dispcc-sc7180.c

+0 −19
Original line number Original line Diff line number Diff line
@@ -592,24 +592,6 @@ static struct clk_branch disp_cc_mdss_rot_clk = { 
	},

	},

};

};





static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {

	.halt_reg = 0x400c,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x400c,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_mdss_rscc_ahb_clk",

			.parent_data = &(const struct clk_parent_data){

				.hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {

static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {

	.halt_reg = 0x4008,

	.halt_reg = 0x4008,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT,
@@ -687,7 +669,6 @@ static struct clk_regmap *disp_cc_sc7180_clocks[] = { 
	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,

	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,

	[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,

	[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,

	[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,

	[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,

	[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,

	[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,

	[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,

	[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,

	[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,

	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,

	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,

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